From patchwork Tue Apr 19 10:07:33 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Wilson X-Patchwork-Id: 8878611 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id CFC3CBF29F for ; Tue, 19 Apr 2016 10:07:52 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id DF62E2022A for ; Tue, 19 Apr 2016 10:07:51 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id C297620225 for ; Tue, 19 Apr 2016 10:07:50 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 059FC6E2BE; Tue, 19 Apr 2016 10:07:50 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-wm0-x243.google.com (mail-wm0-x243.google.com [IPv6:2a00:1450:400c:c09::243]) by gabe.freedesktop.org (Postfix) with ESMTPS id 34E376E122 for ; Tue, 19 Apr 2016 10:07:48 +0000 (UTC) Received: by mail-wm0-x243.google.com with SMTP id l6so3658369wml.3 for ; Tue, 19 Apr 2016 03:07:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=6vx3NG8VSeTdqmYYNyUSA3ZT5zF+2yFIgNESM1luxrQ=; b=b2yZ10X/jFFx2YM15RY05aPkD53O4Lsfz+9pp0E2ZMWIC1qOtC047SDWmcpagcVu/E eQlc06cSoTqC4Zi7EXqvs7nEZylhg1zPG50c26btky8k26ZME2PsFNkF8YxVsmMtIIo+ aqEPLzXiupFP9LVqk+QhfeqYsxgnh/Tz8SDsfVWJS62+A4Y9CTjBeTyLOegPyYUhx0+r zYjRckJOBfLWNvA716Fu+0eXaruF/8ioKC3H+LCecTIrYFSizmsUTfbRJZhql2iYEDtd CDlE2vSjzfvgRdwyucewrjZVfq6DTcTAd37Y7NzN2GcEUKnEChW9dKjmO82kZPWdWAtD MMFw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=6vx3NG8VSeTdqmYYNyUSA3ZT5zF+2yFIgNESM1luxrQ=; b=gOp3xj3yqVbiRqyN6DdRA1oKeRnn1ESx8WHA9kyQe0V/3n5d8ZP6fd2PtgsZvMh+Ll hEi9oTcEhRpjM2IpCML1R1wl+QJgY9v9UB0xmynCEXLImNdR9WKg0oS4ss+JXP7Fn4uK oOEOhr08rvD3WHm8NYvYS3DkzvUNd7oWh8SDYchr82vbc25r0u0tnYYiSnzmESohJHlq VTrmwol0G4e8LM6crgZAIim3y2LeM7Qy6fo3PVg+GTkymNjZH8Y6c+XhySkbZHK4a9ul GTTajdLQWMzR1aYyykXLWwGhmuhFoC65ToSNgjP3gHalFUWAiWYM+reE/CjzO5i7tuYW d85w== X-Gm-Message-State: AOPr4FUA0c59aqiYANI/rVUONj3+LOIPP78rlEM06iWbEvvmcVRoAzKDgHALgT/FF+vmUQ== X-Received: by 10.28.134.67 with SMTP id i64mr22528497wmd.83.1461060466483; Tue, 19 Apr 2016 03:07:46 -0700 (PDT) Received: from haswell.alporthouse.com ([78.156.65.138]) by smtp.gmail.com with ESMTPSA id j10sm68806783wjb.46.2016.04.19.03.07.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 19 Apr 2016 03:07:45 -0700 (PDT) From: Chris Wilson To: intel-gfx@lists.freedesktop.org Date: Tue, 19 Apr 2016 11:07:33 +0100 Message-Id: <1461060455-14098-1-git-send-email-chris@chris-wilson.co.uk> X-Mailer: git-send-email 2.8.0.rc3 In-Reply-To: <5715FD43.9050506@linux.intel.com> References: <5715FD43.9050506@linux.intel.com> Subject: [Intel-gfx] [PATCH 1/3] drm/i915: L3 cache remapping is part of context switching X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-5.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Move the i915_gem_l3_remap function such that it next to the context switching, which is where we perform the L3 remap. Signed-off-by: Chris Wilson Reviewed-by: Tvrtko Ursulin --- drivers/gpu/drm/i915/i915_gem.c | 31 ------------------------------- drivers/gpu/drm/i915/i915_gem_context.c | 31 +++++++++++++++++++++++++++++++ 2 files changed, 31 insertions(+), 31 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 9ff73bf0e4ea..59419f10e76a 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -4729,37 +4729,6 @@ err: return ret; } -int i915_gem_l3_remap(struct drm_i915_gem_request *req, int slice) -{ - struct intel_engine_cs *engine = req->engine; - struct drm_device *dev = engine->dev; - struct drm_i915_private *dev_priv = dev->dev_private; - u32 *remap_info = dev_priv->l3_parity.remap_info[slice]; - int i, ret; - - if (!HAS_L3_DPF(dev) || !remap_info) - return 0; - - ret = intel_ring_begin(req, GEN7_L3LOG_SIZE / 4 * 3); - if (ret) - return ret; - - /* - * Note: We do not worry about the concurrent register cacheline hang - * here because no other code should access these registers other than - * at initialization time. - */ - for (i = 0; i < GEN7_L3LOG_SIZE / 4; i++) { - intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(1)); - intel_ring_emit_reg(engine, GEN7_L3LOG(slice, i)); - intel_ring_emit(engine, remap_info[i]); - } - - intel_ring_advance(engine); - - return ret; -} - void i915_gem_init_swizzling(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c index 59d66b5bc8ad..68232d384902 100644 --- a/drivers/gpu/drm/i915/i915_gem_context.c +++ b/drivers/gpu/drm/i915/i915_gem_context.c @@ -643,6 +643,37 @@ mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags) return ret; } +int i915_gem_l3_remap(struct drm_i915_gem_request *req, int slice) +{ + struct intel_engine_cs *engine = req->engine; + struct drm_device *dev = engine->dev; + struct drm_i915_private *dev_priv = dev->dev_private; + u32 *remap_info = dev_priv->l3_parity.remap_info[slice]; + int i, ret; + + if (!HAS_L3_DPF(dev) || !remap_info) + return 0; + + ret = intel_ring_begin(req, GEN7_L3LOG_SIZE / 4 * 3); + if (ret) + return ret; + + /* + * Note: We do not worry about the concurrent register cacheline hang + * here because no other code should access these registers other than + * at initialization time. + */ + for (i = 0; i < GEN7_L3LOG_SIZE / 4; i++) { + intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(1)); + intel_ring_emit_reg(engine, GEN7_L3LOG(slice, i)); + intel_ring_emit(engine, remap_info[i]); + } + + intel_ring_advance(engine); + + return ret; +} + static inline bool skip_rcs_switch(struct intel_engine_cs *engine, struct intel_context *to) {