| Message ID | 1461237820-19195-1-git-send-email-tim.gore@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 4/21/2016 12:23 PM, tim.gore@intel.com wrote: > From: Tim Gore <tim.gore@intel.com> > > This patch applies a performance enhancement workaround > based on analysis of DX and OCL S-Curve workloads. We > increase the General Priority Credits for L3SQ from the > hardware default of 56 to the max value 62, and decrease > the High Priority credits from 8 to 2. > > v2: Only apply to B0 onwards > > v3: Move w/a to per engine init, ie bxt_init_workarounds > > Signed-off-by: Tim Gore <tim.gore@intel.com> > --- > drivers/gpu/drm/i915/i915_reg.h | 1 + > drivers/gpu/drm/i915/intel_ringbuffer.c | 4 ++++ > 2 files changed, 5 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index c21b71c..efd36c3 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -6074,6 +6074,7 @@ enum skl_disp_power_wells { > > #define GEN8_L3SQCREG1 _MMIO(0xB100) > #define BDW_WA_L3SQCREG1_DEFAULT 0x784000 > +#define BXT_WA_L3SQCREG1_DEFAULT 0xF84000 > > #define GEN7_L3CNTLREG1 _MMIO(0xB01C) > #define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C47FF8C > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c > index 245386e..f6e8e7e 100644 > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > @@ -1180,6 +1180,10 @@ static int bxt_init_workarounds(struct intel_engine_cs *engine) > return ret; > } > > + /* WaProgramL3SqcReg1DefaultForPerf:bxt */ > + if (IS_BXT_REVID(dev, BXT_REVID_B0, REVID_FOREVER)) > + I915_WRITE(GEN8_L3SQCREG1, BXT_WA_L3SQCREG1_DEFAULT); > + > return 0; > } > > lgtm, Reviewed-by: Michel Thierry <michel.thierry@intel.com>
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index c21b71c..efd36c3 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -6074,6 +6074,7 @@ enum skl_disp_power_wells { #define GEN8_L3SQCREG1 _MMIO(0xB100) #define BDW_WA_L3SQCREG1_DEFAULT 0x784000 +#define BXT_WA_L3SQCREG1_DEFAULT 0xF84000 #define GEN7_L3CNTLREG1 _MMIO(0xB01C) #define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C47FF8C diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 245386e..f6e8e7e 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -1180,6 +1180,10 @@ static int bxt_init_workarounds(struct intel_engine_cs *engine) return ret; } + /* WaProgramL3SqcReg1DefaultForPerf:bxt */ + if (IS_BXT_REVID(dev, BXT_REVID_B0, REVID_FOREVER)) + I915_WRITE(GEN8_L3SQCREG1, BXT_WA_L3SQCREG1_DEFAULT); + return 0; }