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[v3] drm/i915:bxt: implement WaProgramL3SqcReg1DefaultForPerf

Message ID 1461314761-36854-1-git-send-email-tim.gore@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

tim.gore@intel.com April 22, 2016, 8:46 a.m. UTC 
From: Tim Gore <tim.gore@intel.com>

This patch applies a performance enhancement workaround
based on analysis of DX and OCL S-Curve workloads. We
increase the General Priority Credits for L3SQ from the
hardware default of 56 to the max value 62, and decrease
the High Priority credits from 8 to 2.

v2: Only apply to B0 onwards

v3: Move w/a to per engine init, ie bxt_init_workarounds

Signed-off-by: Tim Gore <tim.gore@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h         | 1 +
 drivers/gpu/drm/i915/intel_ringbuffer.c | 4 ++++
 2 files changed, 5 insertions(+)

Comments

Tvrtko Ursulin April 25, 2016, 9:09 a.m. UTC | #1 
On 24/04/16 07:23, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915:bxt: implement WaProgramL3SqcReg1DefaultForPerf (rev4)
> URL   : https://patchwork.freedesktop.org/series/5990/
> State : success
>
> == Summary ==
>
> Series 5990v4 drm/i915:bxt: implement WaProgramL3SqcReg1DefaultForPerf
> http://patchwork.freedesktop.org/api/1.0/series/5990/revisions/4/mbox/
>
>
> bdw-ultra        total:193  pass:170  dwarn:0   dfail:0   fail:0   skip:23
> bsw-nuc-2        total:192  pass:153  dwarn:0   dfail:0   fail:0   skip:39
> byt-nuc          total:192  pass:154  dwarn:0   dfail:0   fail:0   skip:38
> ilk-hp8440p      total:193  pass:136  dwarn:0   dfail:0   fail:0   skip:57
> ivb-t430s        total:193  pass:165  dwarn:0   dfail:0   fail:0   skip:28
> skl-i7k-2        total:193  pass:168  dwarn:0   dfail:0   fail:0   skip:25
> skl-nuci5        total:193  pass:182  dwarn:0   dfail:0   fail:0   skip:11
> snb-dellxps      total:193  pass:155  dwarn:0   dfail:0   fail:0   skip:38
>
> Results at /archive/results/CI_IGT_test/Patchwork_2028/
>
> 340c485ad98d0ec0369a3b18d4a09938f3f5537d drm-intel-nightly: 2016y-04m-22d-17h-32m-25s UTC integration manifest
> 22517b8 drm/i915:bxt: implement WaProgramL3SqcReg1DefaultForPerf
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx


Merged, thanks for the patch and review.

Regards,

Tvrtko
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Patch

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c21b71c..efd36c3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6074,6 +6074,7 @@  enum skl_disp_power_wells {
 
 #define GEN8_L3SQCREG1				_MMIO(0xB100)
 #define  BDW_WA_L3SQCREG1_DEFAULT		0x784000
+#define  BXT_WA_L3SQCREG1_DEFAULT		0xF84000
 
 #define GEN7_L3CNTLREG1				_MMIO(0xB01C)
 #define  GEN7_WA_FOR_GEN7_L3_CONTROL			0x3C47FF8C
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 245386e..f6e8e7e 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1180,6 +1180,10 @@  static int bxt_init_workarounds(struct intel_engine_cs *engine)
 			return ret;
 	}
 
+	/* WaProgramL3SqcReg1DefaultForPerf:bxt */
+	if (IS_BXT_REVID(dev, BXT_REVID_B0, REVID_FOREVER))
+		I915_WRITE(GEN8_L3SQCREG1, BXT_WA_L3SQCREG1_DEFAULT);
+
 	return 0;
 }