From patchwork Sun Apr 24 07:18:47 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Wilson X-Patchwork-Id: 8919841 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id B4923BF440 for ; Sun, 24 Apr 2016 07:22:46 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id A4278201FA for ; Sun, 24 Apr 2016 07:22:45 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id ABFB3201EC for ; Sun, 24 Apr 2016 07:22:44 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0CCAD6E140; Sun, 24 Apr 2016 07:22:41 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-wm0-x243.google.com (mail-wm0-x243.google.com [IPv6:2a00:1450:400c:c09::243]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5712A6E123 for ; Sun, 24 Apr 2016 07:19:29 +0000 (UTC) Received: by mail-wm0-x243.google.com with SMTP id n3so16107164wmn.1 for ; Sun, 24 Apr 2016 00:19:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=t1SQM7FxOX6Zx2FM6xdg4UShqqjPYyasZaWwG7in8d0=; b=SZdGn+7JJy+aFwLDo06ED6rOpjFDqdTFVptotvVjop6Tbc4HFlhI1QRe0NevPSt+NR pxno/WoLDo1GpW8hzWYtoKuh8KUQ1ArJ9P5WskziRDemMtp/zcMyC3uldJ5Ra2LLQZTp H+P8hrEpFI5SkNKLLVak1Rytd4iYXOaARhVFF3P/uaTFLjCTvcn7+sP1kQl4xiCAmgbK 4ZZBRn01ZmMgAs/qVYj2OnUuMTFRipVHT4RMesJHqlWg6yFYnSPM+HnIlcStIIVyuqks rtfYv/dvkb5KPw2zci0EStl5Ua9Fg4401B7FRMdPvGs2e3LIza7SYElaYElPg2O9+tZv ahjQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=t1SQM7FxOX6Zx2FM6xdg4UShqqjPYyasZaWwG7in8d0=; b=DWaqhSgQGfMAq75RnIGKeUhrntyDniivSXU83ioaaf2KvGEJD9vV/FjiOwjv4prRwL QQ1Y2qiufp2VaKV40yil3Uetbr1aNn+nu4F9l1MxYPlSGHZ8ZmoFEdBlZd0cGGpfZAXF OTOaMXA0wBC6QQrGbofeBoX7FFezmE4at6j+yJqw9oHH5L3olG9ZELaJrWAuPoIRHx64 xsIAj1nTX9J6FixVutZcWDSQlTIeOr6GOdc/4+AWtebr0jbfnsbJrb/n4eCngq3NUf19 pVmdk8vUb+/CEohV1LQ9FWi85mqI+y54qu/5c+btbNzyA796RQJuBKHxfyOr8MHeA4Is aO5Q== X-Gm-Message-State: AOPr4FU+HDFCxT4IMjMEKSVvqT0vpDZ8a3hZanWlW7jsP7kjfCMAK7E/ezGHpzM7ssgYhg== X-Received: by 10.28.129.22 with SMTP id c22mr5029955wmd.89.1461482367753; Sun, 24 Apr 2016 00:19:27 -0700 (PDT) Received: from haswell.alporthouse.com ([78.156.65.138]) by smtp.gmail.com with ESMTPSA id i11sm16937119wjn.36.2016.04.24.00.19.26 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 24 Apr 2016 00:19:26 -0700 (PDT) From: Chris Wilson To: intel-gfx@lists.freedesktop.org Date: Sun, 24 Apr 2016 08:18:47 +0100 Message-Id: <1461482332-21975-16-git-send-email-chris@chris-wilson.co.uk> X-Mailer: git-send-email 2.8.1 In-Reply-To: <1461482332-21975-1-git-send-email-chris@chris-wilson.co.uk> References: <1461482332-21975-1-git-send-email-chris@chris-wilson.co.uk> Subject: [Intel-gfx] [PATCH 16/21] drm/i915: Move the magical deferred context allocation into the request X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-5.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP We can hide more details of execlists from higher level code by removing the explicit call to create an execlist context from execbuffer and into its first use by execlists. Signed-off-by: Chris Wilson Reviewed-by: Tvrtko Ursulin --- drivers/gpu/drm/i915/i915_gem_execbuffer.c | 8 -------- drivers/gpu/drm/i915/intel_lrc.c | 23 +++++++++++++++-------- drivers/gpu/drm/i915/intel_lrc.h | 2 -- 3 files changed, 15 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c index 6f4f2a6cdf93..e0ee5d1ac372 100644 --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c @@ -1085,14 +1085,6 @@ i915_gem_validate_context(struct drm_device *dev, struct drm_file *file, return ERR_PTR(-EIO); } - if (i915.enable_execlists && !ctx->engine[engine->id].state) { - int ret = intel_lr_context_deferred_alloc(ctx, engine); - if (ret) { - DRM_DEBUG("Could not create LRC %u: %d\n", ctx_id, ret); - return ERR_PTR(ret); - } - } - return ctx; } diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index eeb8be695288..23bc5fca6595 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -227,6 +227,8 @@ enum { #define GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x17 #define GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x26 +static int execlists_context_deferred_alloc(struct intel_context *ctx, + struct intel_engine_cs *engine); static int intel_lr_context_pin(struct intel_context *ctx, struct intel_engine_cs *engine); @@ -675,8 +677,6 @@ int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request struct intel_engine_cs *engine = request->engine; int ret; - request->ringbuf = request->ctx->engine[engine->id].ringbuf; - if (i915.enable_guc_submission) { /* * Check that the GuC has space for the request before @@ -690,6 +690,14 @@ int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request return ret; } + if (request->ctx->engine[engine->id].state == NULL) { + ret = execlists_context_deferred_alloc(request->ctx, engine); + if (ret) + return ret; + } + + request->ringbuf = request->ctx->engine[engine->id].ringbuf; + ret = intel_lr_context_pin(request->ctx, engine); if (ret) return ret; @@ -2134,7 +2142,7 @@ logical_ring_init(struct drm_device *dev, struct intel_engine_cs *engine) if (ret) goto error; - ret = intel_lr_context_deferred_alloc(dctx, engine); + ret = execlists_context_deferred_alloc(dctx, engine); if (ret) goto error; @@ -2608,9 +2616,9 @@ uint32_t intel_lr_context_size(struct intel_engine_cs *engine) } /** - * intel_lr_context_deferred_alloc() - create the LRC specific bits of a context + * execlists_context_deferred_alloc() - create the LRC specific bits of a context * @ctx: LR context to create. - * @ring: engine to be used with the context. + * @engine: engine to be used with the context. * * This function can be called more than once, with different engines, if we plan * to use the context with them. The context backing objects and the ringbuffers @@ -2620,9 +2628,8 @@ uint32_t intel_lr_context_size(struct intel_engine_cs *engine) * * Return: non-zero on error. */ - -int intel_lr_context_deferred_alloc(struct intel_context *ctx, - struct intel_engine_cs *engine) +static int execlists_context_deferred_alloc(struct intel_context *ctx, + struct intel_engine_cs *engine) { struct drm_device *dev = engine->dev; struct drm_i915_gem_object *ctx_obj; diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h index b17ab79333aa..8bea937973f6 100644 --- a/drivers/gpu/drm/i915/intel_lrc.h +++ b/drivers/gpu/drm/i915/intel_lrc.h @@ -102,8 +102,6 @@ static inline void intel_logical_ring_emit_reg(struct intel_ringbuffer *ringbuf, void intel_lr_context_free(struct intel_context *ctx); uint32_t intel_lr_context_size(struct intel_engine_cs *engine); -int intel_lr_context_deferred_alloc(struct intel_context *ctx, - struct intel_engine_cs *engine); void intel_lr_context_unpin(struct intel_context *ctx, struct intel_engine_cs *engine);