From patchwork Tue Apr 26 20:06:04 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Wilson X-Patchwork-Id: 8944221 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 2839ABF29F for ; Tue, 26 Apr 2016 20:06:54 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 4DC58200FE for ; Tue, 26 Apr 2016 20:06:53 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 71AAB20138 for ; Tue, 26 Apr 2016 20:06:52 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 012D86E93A; Tue, 26 Apr 2016 20:06:46 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-wm0-x242.google.com (mail-wm0-x242.google.com [IPv6:2a00:1450:400c:c09::242]) by gabe.freedesktop.org (Postfix) with ESMTPS id 34B866E93A for ; Tue, 26 Apr 2016 20:06:43 +0000 (UTC) Received: by mail-wm0-x242.google.com with SMTP id r12so7341301wme.0 for ; Tue, 26 Apr 2016 13:06:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=CU0XQR8+J/TVOUvXg6ispMBLSg8Q6JKFzst8o0DutVQ=; b=MeSUNPW96d52JvwLXIrgX5+/MGqfhDV/RcXqQyuWLKPHty8qvltlRZhVq2qTM5hA04 Lin6SXeeQxqK0QDdzZ4GGL6WTXoKTxmAbuq4aYlk5hIxM2CfaavdKKIucerOOkqAbxBX xn/F6SLp09Xfd6sGIVyfiJ49dl282fpQzSWCb1+83EGt65ivC2SM8RsPdy/vlLXKepav UGOGW3rQH49QuPayHaXe1hq6sP+0nnC4LU/N/TcJ4bElkTXR/m1Y8AthXkZHwN1nFmmg WHUi6Spqu1meWj/TXDH+PaHwkmm0uSoZRD4WMNY+R9EbMGfK5mglU94mMMpexxyjd65h PrKQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=CU0XQR8+J/TVOUvXg6ispMBLSg8Q6JKFzst8o0DutVQ=; b=IZSiI9MbaiiVzyF3d175SY8Y/yMqmRMiYmCGcU+H5lQK/wlI3gYvthv15khdGAdknT uH6tRz0D0FNJskyMvQ6bAjaU83KbC5Ems9s7Tpk54COhRQJU5AiqwJH2N94h8wFhg+B6 rvOlIIPxfms/VeeRSQd0FZcafjlZVbwqUtc7v3q+5eHaxx9vptOivTS1QK77KGnYTqx7 Qu0Z2GsLpDsMDRHBECxUWoN1k3UV8KiJHO6im91leM7DL+g4ZnsoyW1ia0j3HR2K8+xI EdVkF5/B0hxlv6IFXgZph6oRNU5fQVbmW1SHn4ImLNdw+uFHhG3lFqNtC3V+QOXQGIgq dEcQ== X-Gm-Message-State: AOPr4FV58usiMKgiPC2uzAFf14eG8rV+7LxXNmxBRcgJgVT2Se2QYtoad5bae8/XkQT75A== X-Received: by 10.28.150.142 with SMTP id y136mr20819367wmd.28.1461701200778; Tue, 26 Apr 2016 13:06:40 -0700 (PDT) Received: from haswell.alporthouse.com ([78.156.65.138]) by smtp.gmail.com with ESMTPSA id gk4sm347603wjd.7.2016.04.26.13.06.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 26 Apr 2016 13:06:39 -0700 (PDT) From: Chris Wilson To: intel-gfx@lists.freedesktop.org Date: Tue, 26 Apr 2016 21:06:04 +0100 Message-Id: <1461701180-895-10-git-send-email-chris@chris-wilson.co.uk> X-Mailer: git-send-email 2.8.1 In-Reply-To: <1461701180-895-1-git-send-email-chris@chris-wilson.co.uk> References: <1461701180-895-1-git-send-email-chris@chris-wilson.co.uk> Subject: [Intel-gfx] [PATCH v6 09/25] drm/i915: Consolidate L3 remapping LRI X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-5.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP We can use a single MI_LOAD_REGISTER_IMM command packet to write all the L3 remapping registers, shrinking the number of bytes required to emit the context switch. Signed-off-by: Chris Wilson Cc: Tvrtko Ursulin Reviewed-by: Tvrtko Ursulin --- drivers/gpu/drm/i915/i915_gem_context.c | 16 +++++++--------- 1 file changed, 7 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c index a429b4dcb4de..373bad8ee04c 100644 --- a/drivers/gpu/drm/i915/i915_gem_context.c +++ b/drivers/gpu/drm/i915/i915_gem_context.c @@ -603,16 +603,14 @@ mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags) int i915_gem_l3_remap(struct drm_i915_gem_request *req, int slice) { + u32 *remap_info = req->i915->l3_parity.remap_info[slice]; struct intel_engine_cs *engine = req->engine; - struct drm_device *dev = engine->dev; - struct drm_i915_private *dev_priv = dev->dev_private; - u32 *remap_info = dev_priv->l3_parity.remap_info[slice]; int i, ret; - if (!HAS_L3_DPF(dev) || !remap_info) + if (!remap_info) return 0; - ret = intel_ring_begin(req, GEN7_L3LOG_SIZE / 4 * 3); + ret = intel_ring_begin(req, GEN7_L3LOG_SIZE/4 * 2 + 2); if (ret) return ret; @@ -621,15 +619,15 @@ int i915_gem_l3_remap(struct drm_i915_gem_request *req, int slice) * here because no other code should access these registers other than * at initialization time. */ - for (i = 0; i < GEN7_L3LOG_SIZE / 4; i++) { - intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(1)); + intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(GEN7_L3LOG_SIZE/4)); + for (i = 0; i < GEN7_L3LOG_SIZE/4; i++) { intel_ring_emit_reg(engine, GEN7_L3LOG(slice, i)); intel_ring_emit(engine, remap_info[i]); } - + intel_ring_emit(engine, MI_NOOP); intel_ring_advance(engine); - return ret; + return 0; } static inline bool skip_rcs_switch(struct intel_engine_cs *engine,