From patchwork Tue May 3 11:46:36 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kahola, Mika" X-Patchwork-Id: 9003041 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id A4F5D9F65D for ; Tue, 3 May 2016 11:46:54 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id BCA7C200CC for ; Tue, 3 May 2016 11:46:53 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id C6B7E2024F for ; Tue, 3 May 2016 11:46:52 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 68E966E36C; Tue, 3 May 2016 11:46:50 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id 9E3776E787; Tue, 3 May 2016 11:46:49 +0000 (UTC) Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga101.jf.intel.com with ESMTP; 03 May 2016 04:46:42 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.24,572,1455004800"; d="scan'208";a="96238650" Received: from sorvi.fi.intel.com ([10.237.72.50]) by fmsmga004.fm.intel.com with ESMTP; 03 May 2016 04:46:40 -0700 From: Mika Kahola To: intel-gfx@lists.freedesktop.org Date: Tue, 3 May 2016 14:46:36 +0300 Message-Id: <1462275998-4864-2-git-send-email-mika.kahola@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1462275998-4864-1-git-send-email-mika.kahola@intel.com> References: <1462275998-4864-1-git-send-email-mika.kahola@intel.com> Cc: dri-devel@lists.freedesktop.org Subject: [Intel-gfx] [PATCH 1/3] drm/i915: Check pixel rate for DP to VGA dongle X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-5.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Prep work to improve DP branch device handling. Filter out a mode that exceeds the max pixel rate setting for DP to VGA dongle. This is defined in DPCD register 0x81 if detailed cap info i.e. info field is 4 bytes long and it is available for DP downstream port. The register defines the pixel rate divided by 8 in MP/s. Signed-off-by: Mika Kahola --- drivers/gpu/drm/i915/intel_dp.c | 34 ++++++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_drv.h | 9 +++++++++ 2 files changed, 43 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 3633002..74a04ce 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -201,6 +201,13 @@ intel_dp_mode_valid(struct drm_connector *connector, int max_rate, mode_rate, max_lanes, max_link_clock; int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; + /* DP to VGA dongle may define max pixel rate in DPCD */ + if (intel_dp->dfp.present && + intel_dp->dfp.detailed_cap_info && + (intel_dp->dfp.type & DP_DS_PORT_TYPE_VGA) && + (intel_dp->dfp.dot_clk > 0)) + max_dotclk = min(max_dotclk, intel_dp->dfp.dot_clk); + if (is_edp(intel_dp) && fixed_mode) { if (mode->hdisplay > fixed_mode->hdisplay) return MODE_PANEL; @@ -4566,6 +4573,28 @@ static const struct drm_encoder_funcs intel_dp_enc_funcs = { .destroy = intel_dp_encoder_destroy, }; +static void intel_dp_get_dfp(struct intel_dp *intel_dp) +{ + uint8_t dfp_info[4]; + + intel_dp->dfp.detailed_cap_info = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE; + + if (drm_dp_dpcd_read(&intel_dp->aux, DP_DOWNSTREAM_PORT_0, dfp_info, 4) < 0) { + intel_dp->dfp.present = false; + intel_dp->dfp.detailed_cap_info = false; + return; /* aux transfer failed */ + } + + intel_dp->dfp.type = dfp_info[0] & DP_DS_PORT_TYPE_MASK; + + if (intel_dp->dfp.detailed_cap_info) { + if (intel_dp->dfp.type & DP_DS_PORT_TYPE_VGA) { + intel_dp->dfp.dot_clk = dfp_info[1] * 8 * 1000; + DRM_DEBUG_KMS("max pixel rate for VGA is %d kHz\n", intel_dp->dfp.dot_clk); + } + } +} + enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd) { @@ -4599,6 +4628,11 @@ intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd) power_domain = intel_display_port_aux_power_domain(intel_encoder); intel_display_power_get(dev_priv, power_domain); + intel_dp->dfp.present = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & 0x1; + + if (intel_dp->dfp.present) + intel_dp_get_dfp(intel_dp); + if (long_hpd) { /* indicate that we need to restart link training */ intel_dp->train_set_valid = false; diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 21dee3f..9798a59 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -794,6 +794,13 @@ enum link_m_n_set { M2_N2 }; +struct intel_dp_dfp { + bool present; + int type; + bool detailed_cap_info; + int dot_clk; /* pixel rate for VGA dongles */ +}; + struct intel_dp { i915_reg_t output_reg; i915_reg_t aux_ch_ctl_reg; @@ -861,6 +868,8 @@ struct intel_dp { bool train_set_valid; + struct intel_dp_dfp dfp; + /* Displayport compliance testing */ unsigned long compliance_test_type; unsigned long compliance_test_data;