diff mbox

[04/12] drm/i915: Pass around plane_state instead of fb+rotation

Message ID 1462290001-9246-5-git-send-email-ville.syrjala@linux.intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Ville Syrjälä May 3, 2016, 3:39 p.m. UTC 
From: Ville Syrjälä <ville.syrjala@linux.intel.com>

intel_compute_tile_offset() and intel_add_fb_offsets() get passed the fb
and the rotation. As both of those come from the plane state we can just
pass that in instead.

For extra consitency pass the plane state to intel_fb_xy_to_linear() as
well even though it only really needs the fb.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_display.c | 35 ++++++++++++++++++++---------------
 drivers/gpu/drm/i915/intel_drv.h     |  9 ++++-----
 drivers/gpu/drm/i915/intel_sprite.c  | 22 +++++++++++-----------
 3 files changed, 35 insertions(+), 31 deletions(-)

Comments

Sivakumar Thulasimani May 5, 2016, 8:21 a.m. UTC | #1 
Reviewed-by: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>

On 5/3/2016 9:09 PM, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> intel_compute_tile_offset() and intel_add_fb_offsets() get passed the fb
> and the rotation. As both of those come from the plane state we can just
> pass that in instead.
>
> For extra consitency pass the plane state to intel_fb_xy_to_linear() as
> well even though it only really needs the fb.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> ---
>   drivers/gpu/drm/i915/intel_display.c | 35 ++++++++++++++++++++---------------
>   drivers/gpu/drm/i915/intel_drv.h     |  9 ++++-----
>   drivers/gpu/drm/i915/intel_sprite.c  | 22 +++++++++++-----------
>   3 files changed, 35 insertions(+), 31 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 87b783c56533..b8ca6bc3595c 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2314,8 +2314,10 @@ static int intel_fb_pitch(const struct drm_framebuffer *fb, int plane,
>    * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
>    */
>   u32 intel_fb_xy_to_linear(int x, int y,
> -			  const struct drm_framebuffer *fb, int plane)
> +			  const struct intel_plane_state *state,
> +			  int plane)
>   {
> +	const struct drm_framebuffer *fb = state->base.fb;
>   	unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
>   	unsigned int pitch = fb->pitches[plane];
>   
> @@ -2328,11 +2330,12 @@ u32 intel_fb_xy_to_linear(int x, int y,
>    * specify the start of scanout from the beginning of the gtt mapping.
>    */
>   void intel_add_fb_offsets(int *x, int *y,
> -			  const struct drm_framebuffer *fb, int plane,
> -			  unsigned int rotation)
> +			  const struct intel_plane_state *state,
> +			  int plane)
>   
>   {
> -	const struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
> +	const struct intel_framebuffer *intel_fb = to_intel_framebuffer(state->base.fb);
> +	unsigned int rotation = state->base.rotation;
>   
>   	if (intel_rotation_90_or_270(rotation)) {
>   		*x += intel_fb->rotated[plane].x;
> @@ -2439,10 +2442,12 @@ static u32 _intel_compute_tile_offset(const struct drm_i915_private *dev_priv,
>   }
>   
>   u32 intel_compute_tile_offset(int *x, int *y,
> -			      const struct drm_framebuffer *fb, int plane,
> -			      unsigned int rotation)
> +			      const struct intel_plane_state *state,
> +			      int plane)
>   {
> -	const struct drm_i915_private *dev_priv = to_i915(fb->dev);
> +	const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev);
> +	const struct drm_framebuffer *fb = state->base.fb;
> +	unsigned int rotation = state->base.rotation;
>   	u32 alignment = intel_surf_alignment(dev_priv, fb->modifier[plane]);
>   	int pitch = intel_fb_pitch(fb, plane, rotation);
>   
> @@ -2867,11 +2872,11 @@ static void i9xx_update_primary_plane(struct drm_plane *primary,
>   	if (IS_G4X(dev))
>   		dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
>   
> -	intel_add_fb_offsets(&x, &y, fb, 0, rotation);
> +	intel_add_fb_offsets(&x, &y, plane_state, 0);
>   
>   	if (INTEL_INFO(dev)->gen >= 4)
>   		intel_crtc->dspaddr_offset =
> -			intel_compute_tile_offset(&x, &y, fb, 0, rotation);
> +			intel_compute_tile_offset(&x, &y, plane_state, 0);
>   
>   	if (rotation == BIT(DRM_ROTATE_180)) {
>   		dspcntr |= DISPPLANE_ROTATE_180;
> @@ -2880,7 +2885,7 @@ static void i9xx_update_primary_plane(struct drm_plane *primary,
>   		y += (crtc_state->pipe_src_h - 1);
>   	}
>   
> -	linear_offset = intel_fb_xy_to_linear(x, y, fb, 0);
> +	linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
>   
>   	if (INTEL_INFO(dev)->gen < 4)
>   		intel_crtc->dspaddr_offset = linear_offset;
> @@ -2970,10 +2975,10 @@ static void ironlake_update_primary_plane(struct drm_plane *primary,
>   	if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
>   		dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
>   
> -	intel_add_fb_offsets(&x, &y, fb, 0, rotation);
> +	intel_add_fb_offsets(&x, &y, plane_state, 0);
>   
>   	intel_crtc->dspaddr_offset =
> -		intel_compute_tile_offset(&x, &y, fb, 0, rotation);
> +		intel_compute_tile_offset(&x, &y, plane_state, 0);
>   
>   	if (rotation == BIT(DRM_ROTATE_180)) {
>   		dspcntr |= DISPPLANE_ROTATE_180;
> @@ -2984,7 +2989,7 @@ static void ironlake_update_primary_plane(struct drm_plane *primary,
>   		}
>   	}
>   
> -	linear_offset = intel_fb_xy_to_linear(x, y, fb, 0);
> +	linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
>   
>   	intel_crtc->adjusted_x = x;
>   	intel_crtc->adjusted_y = y;
> @@ -3211,8 +3216,8 @@ static void skylake_update_primary_plane(struct drm_plane *plane,
>   		src_h = drm_rect_height(&r);
>   	}
>   
> -	intel_add_fb_offsets(&src_x, &src_y, fb, 0, rotation);
> -	surf_addr = intel_compute_tile_offset(&src_x, &src_y, fb, 0, rotation);
> +	intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
> +	surf_addr = intel_compute_tile_offset(&src_x, &src_y, plane_state, 0);
>   
>   	/* Sizes are 0 based */
>   	src_w--;
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 42b21c54a646..75e4d59f1ab3 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1126,10 +1126,10 @@ int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
>   extern const struct drm_plane_funcs intel_plane_funcs;
>   void intel_init_display_hooks(struct drm_i915_private *dev_priv);
>   unsigned int intel_fb_xy_to_linear(int x, int y,
> -				   const struct drm_framebuffer *fb, int plane);
> +				   const struct intel_plane_state *state,
> +				   int plane);
>   void intel_add_fb_offsets(int *x, int *y,
> -			  const struct drm_framebuffer *fb, int plane,
> -			  unsigned int rotation);
> +			  const struct intel_plane_state *state, int plane);
>   unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
>   bool intel_has_pending_fb_unpin(struct drm_device *dev);
>   void intel_mark_busy(struct drm_device *dev);
> @@ -1240,8 +1240,7 @@ void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
>   #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
>   #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
>   u32 intel_compute_tile_offset(int *x, int *y,
> -			      const struct drm_framebuffer *fb, int plane,
> -			      unsigned int rotation);
> +			      const struct intel_plane_state *state, int plane);
>   void intel_prepare_reset(struct drm_device *dev);
>   void intel_finish_reset(struct drm_device *dev);
>   void hsw_enable_pc8(struct drm_i915_private *dev_priv);
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> index 22a2ba0c21b0..c7ceb6e56327 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -241,8 +241,8 @@ skl_update_plane(struct drm_plane *drm_plane,
>   		src_h = drm_rect_height(&r);
>   	}
>   
> -	intel_add_fb_offsets(&x, &y, fb, 0, rotation);
> -	surf_addr = intel_compute_tile_offset(&x, &y, fb, 0, rotation);
> +	intel_add_fb_offsets(&x, &y, plane_state, 0);
> +	surf_addr = intel_compute_tile_offset(&x, &y, plane_state, 0);
>   
>   	/* Sizes are 0 based */
>   	src_w--;
> @@ -418,8 +418,8 @@ vlv_update_plane(struct drm_plane *dplane,
>   	crtc_w--;
>   	crtc_h--;
>   
> -	intel_add_fb_offsets(&x, &y, fb, 0, rotation);
> -	sprsurf_offset = intel_compute_tile_offset(&x, &y, fb, 0, rotation);
> +	intel_add_fb_offsets(&x, &y, plane_state, 0);
> +	sprsurf_offset = intel_compute_tile_offset(&x, &y, plane_state, 0);
>   
>   	if (rotation == BIT(DRM_ROTATE_180)) {
>   		sprctl |= SP_ROTATE_180;
> @@ -428,7 +428,7 @@ vlv_update_plane(struct drm_plane *dplane,
>   		y += src_h;
>   	}
>   
> -	linear_offset = intel_fb_xy_to_linear(x, y, fb, 0);
> +	linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
>   
>   	if (key->flags) {
>   		I915_WRITE(SPKEYMINVAL(pipe, plane), key->min_value);
> @@ -549,8 +549,8 @@ ivb_update_plane(struct drm_plane *plane,
>   	if (crtc_w != src_w || crtc_h != src_h)
>   		sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h;
>   
> -	intel_add_fb_offsets(&x, &y, fb, 0, rotation);
> -	sprsurf_offset = intel_compute_tile_offset(&x, &y, fb, 0, rotation);
> +	intel_add_fb_offsets(&x, &y, plane_state, 0);
> +	sprsurf_offset = intel_compute_tile_offset(&x, &y, plane_state, 0);
>   
>   	if (rotation == BIT(DRM_ROTATE_180)) {
>   		sprctl |= SPRITE_ROTATE_180;
> @@ -562,7 +562,7 @@ ivb_update_plane(struct drm_plane *plane,
>   		}
>   	}
>   
> -	linear_offset = intel_fb_xy_to_linear(x, y, fb, 0);
> +	linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
>   
>   	if (key->flags) {
>   		I915_WRITE(SPRKEYVAL(pipe), key->min_value);
> @@ -684,8 +684,8 @@ ilk_update_plane(struct drm_plane *plane,
>   	if (crtc_w != src_w || crtc_h != src_h)
>   		dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h;
>   
> -	intel_add_fb_offsets(&x, &y, fb, 0, rotation);
> -	dvssurf_offset = intel_compute_tile_offset(&x, &y, fb, 0, rotation);
> +	intel_add_fb_offsets(&x, &y, plane_state, 0);
> +	dvssurf_offset = intel_compute_tile_offset(&x, &y, plane_state, 0);
>   
>   	if (rotation == BIT(DRM_ROTATE_180)) {
>   		dvscntr |= DVS_ROTATE_180;
> @@ -694,7 +694,7 @@ ilk_update_plane(struct drm_plane *plane,
>   		y += src_h;
>   	}
>   
> -	linear_offset = intel_fb_xy_to_linear(x, y, fb, 0);
> +	linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
>   
>   	if (key->flags) {
>   		I915_WRITE(DVSKEYVAL(pipe), key->min_value);
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 87b783c56533..b8ca6bc3595c 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2314,8 +2314,10 @@  static int intel_fb_pitch(const struct drm_framebuffer *fb, int plane,
  * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
  */
 u32 intel_fb_xy_to_linear(int x, int y,
-			  const struct drm_framebuffer *fb, int plane)
+			  const struct intel_plane_state *state,
+			  int plane)
 {
+	const struct drm_framebuffer *fb = state->base.fb;
 	unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
 	unsigned int pitch = fb->pitches[plane];
 
@@ -2328,11 +2330,12 @@  u32 intel_fb_xy_to_linear(int x, int y,
  * specify the start of scanout from the beginning of the gtt mapping.
  */
 void intel_add_fb_offsets(int *x, int *y,
-			  const struct drm_framebuffer *fb, int plane,
-			  unsigned int rotation)
+			  const struct intel_plane_state *state,
+			  int plane)
 
 {
-	const struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
+	const struct intel_framebuffer *intel_fb = to_intel_framebuffer(state->base.fb);
+	unsigned int rotation = state->base.rotation;
 
 	if (intel_rotation_90_or_270(rotation)) {
 		*x += intel_fb->rotated[plane].x;
@@ -2439,10 +2442,12 @@  static u32 _intel_compute_tile_offset(const struct drm_i915_private *dev_priv,
 }
 
 u32 intel_compute_tile_offset(int *x, int *y,
-			      const struct drm_framebuffer *fb, int plane,
-			      unsigned int rotation)
+			      const struct intel_plane_state *state,
+			      int plane)
 {
-	const struct drm_i915_private *dev_priv = to_i915(fb->dev);
+	const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev);
+	const struct drm_framebuffer *fb = state->base.fb;
+	unsigned int rotation = state->base.rotation;
 	u32 alignment = intel_surf_alignment(dev_priv, fb->modifier[plane]);
 	int pitch = intel_fb_pitch(fb, plane, rotation);
 
@@ -2867,11 +2872,11 @@  static void i9xx_update_primary_plane(struct drm_plane *primary,
 	if (IS_G4X(dev))
 		dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
 
-	intel_add_fb_offsets(&x, &y, fb, 0, rotation);
+	intel_add_fb_offsets(&x, &y, plane_state, 0);
 
 	if (INTEL_INFO(dev)->gen >= 4)
 		intel_crtc->dspaddr_offset =
-			intel_compute_tile_offset(&x, &y, fb, 0, rotation);
+			intel_compute_tile_offset(&x, &y, plane_state, 0);
 
 	if (rotation == BIT(DRM_ROTATE_180)) {
 		dspcntr |= DISPPLANE_ROTATE_180;
@@ -2880,7 +2885,7 @@  static void i9xx_update_primary_plane(struct drm_plane *primary,
 		y += (crtc_state->pipe_src_h - 1);
 	}
 
-	linear_offset = intel_fb_xy_to_linear(x, y, fb, 0);
+	linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
 
 	if (INTEL_INFO(dev)->gen < 4)
 		intel_crtc->dspaddr_offset = linear_offset;
@@ -2970,10 +2975,10 @@  static void ironlake_update_primary_plane(struct drm_plane *primary,
 	if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
 		dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
 
-	intel_add_fb_offsets(&x, &y, fb, 0, rotation);
+	intel_add_fb_offsets(&x, &y, plane_state, 0);
 
 	intel_crtc->dspaddr_offset =
-		intel_compute_tile_offset(&x, &y, fb, 0, rotation);
+		intel_compute_tile_offset(&x, &y, plane_state, 0);
 
 	if (rotation == BIT(DRM_ROTATE_180)) {
 		dspcntr |= DISPPLANE_ROTATE_180;
@@ -2984,7 +2989,7 @@  static void ironlake_update_primary_plane(struct drm_plane *primary,
 		}
 	}
 
-	linear_offset = intel_fb_xy_to_linear(x, y, fb, 0);
+	linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
 
 	intel_crtc->adjusted_x = x;
 	intel_crtc->adjusted_y = y;
@@ -3211,8 +3216,8 @@  static void skylake_update_primary_plane(struct drm_plane *plane,
 		src_h = drm_rect_height(&r);
 	}
 
-	intel_add_fb_offsets(&src_x, &src_y, fb, 0, rotation);
-	surf_addr = intel_compute_tile_offset(&src_x, &src_y, fb, 0, rotation);
+	intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
+	surf_addr = intel_compute_tile_offset(&src_x, &src_y, plane_state, 0);
 
 	/* Sizes are 0 based */
 	src_w--;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 42b21c54a646..75e4d59f1ab3 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1126,10 +1126,10 @@  int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
 extern const struct drm_plane_funcs intel_plane_funcs;
 void intel_init_display_hooks(struct drm_i915_private *dev_priv);
 unsigned int intel_fb_xy_to_linear(int x, int y,
-				   const struct drm_framebuffer *fb, int plane);
+				   const struct intel_plane_state *state,
+				   int plane);
 void intel_add_fb_offsets(int *x, int *y,
-			  const struct drm_framebuffer *fb, int plane,
-			  unsigned int rotation);
+			  const struct intel_plane_state *state, int plane);
 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
 bool intel_has_pending_fb_unpin(struct drm_device *dev);
 void intel_mark_busy(struct drm_device *dev);
@@ -1240,8 +1240,7 @@  void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
 u32 intel_compute_tile_offset(int *x, int *y,
-			      const struct drm_framebuffer *fb, int plane,
-			      unsigned int rotation);
+			      const struct intel_plane_state *state, int plane);
 void intel_prepare_reset(struct drm_device *dev);
 void intel_finish_reset(struct drm_device *dev);
 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 22a2ba0c21b0..c7ceb6e56327 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -241,8 +241,8 @@  skl_update_plane(struct drm_plane *drm_plane,
 		src_h = drm_rect_height(&r);
 	}
 
-	intel_add_fb_offsets(&x, &y, fb, 0, rotation);
-	surf_addr = intel_compute_tile_offset(&x, &y, fb, 0, rotation);
+	intel_add_fb_offsets(&x, &y, plane_state, 0);
+	surf_addr = intel_compute_tile_offset(&x, &y, plane_state, 0);
 
 	/* Sizes are 0 based */
 	src_w--;
@@ -418,8 +418,8 @@  vlv_update_plane(struct drm_plane *dplane,
 	crtc_w--;
 	crtc_h--;
 
-	intel_add_fb_offsets(&x, &y, fb, 0, rotation);
-	sprsurf_offset = intel_compute_tile_offset(&x, &y, fb, 0, rotation);
+	intel_add_fb_offsets(&x, &y, plane_state, 0);
+	sprsurf_offset = intel_compute_tile_offset(&x, &y, plane_state, 0);
 
 	if (rotation == BIT(DRM_ROTATE_180)) {
 		sprctl |= SP_ROTATE_180;
@@ -428,7 +428,7 @@  vlv_update_plane(struct drm_plane *dplane,
 		y += src_h;
 	}
 
-	linear_offset = intel_fb_xy_to_linear(x, y, fb, 0);
+	linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
 
 	if (key->flags) {
 		I915_WRITE(SPKEYMINVAL(pipe, plane), key->min_value);
@@ -549,8 +549,8 @@  ivb_update_plane(struct drm_plane *plane,
 	if (crtc_w != src_w || crtc_h != src_h)
 		sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h;
 
-	intel_add_fb_offsets(&x, &y, fb, 0, rotation);
-	sprsurf_offset = intel_compute_tile_offset(&x, &y, fb, 0, rotation);
+	intel_add_fb_offsets(&x, &y, plane_state, 0);
+	sprsurf_offset = intel_compute_tile_offset(&x, &y, plane_state, 0);
 
 	if (rotation == BIT(DRM_ROTATE_180)) {
 		sprctl |= SPRITE_ROTATE_180;
@@ -562,7 +562,7 @@  ivb_update_plane(struct drm_plane *plane,
 		}
 	}
 
-	linear_offset = intel_fb_xy_to_linear(x, y, fb, 0);
+	linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
 
 	if (key->flags) {
 		I915_WRITE(SPRKEYVAL(pipe), key->min_value);
@@ -684,8 +684,8 @@  ilk_update_plane(struct drm_plane *plane,
 	if (crtc_w != src_w || crtc_h != src_h)
 		dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h;
 
-	intel_add_fb_offsets(&x, &y, fb, 0, rotation);
-	dvssurf_offset = intel_compute_tile_offset(&x, &y, fb, 0, rotation);
+	intel_add_fb_offsets(&x, &y, plane_state, 0);
+	dvssurf_offset = intel_compute_tile_offset(&x, &y, plane_state, 0);
 
 	if (rotation == BIT(DRM_ROTATE_180)) {
 		dvscntr |= DVS_ROTATE_180;
@@ -694,7 +694,7 @@  ilk_update_plane(struct drm_plane *plane,
 		y += src_h;
 	}
 
-	linear_offset = intel_fb_xy_to_linear(x, y, fb, 0);
+	linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
 
 	if (key->flags) {
 		I915_WRITE(DVSKEYVAL(pipe), key->min_value);