From patchwork Fri May 6 07:50:14 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Wilson X-Patchwork-Id: 9029871 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id AFB749F30C for ; Fri, 6 May 2016 07:50:29 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id C516020389 for ; Fri, 6 May 2016 07:50:28 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 9ADE220382 for ; Fri, 6 May 2016 07:50:27 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 148186E1A4; Fri, 6 May 2016 07:50:27 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-wm0-x243.google.com (mail-wm0-x243.google.com [IPv6:2a00:1450:400c:c09::243]) by gabe.freedesktop.org (Postfix) with ESMTPS id EA0FE6E1A4 for ; Fri, 6 May 2016 07:50:24 +0000 (UTC) Received: by mail-wm0-x243.google.com with SMTP id e201so7630466wme.2 for ; Fri, 06 May 2016 00:50:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=wTHIF3kzHwKHxz6sbdTA6HigpvBZ0MJTrxRLydloFco=; b=c3ta1xyzZeI3ya5lOSu+eotDJBmHddimwJLyfSNu9/w1XZqa2nqrN8D1xk29w4Gttf gbxX+UUC3ZXAMAUIqVVzUbdiu+ISsY/x2BCfyrOAYIRDHM00V5oTh/28eL9NR3feEBK2 L0/PIOe3bPznaJ19St4MS2d+qOHghonZ+poulIDbNtuXe8xiHVChHlWwy/TE7yYZF1xU awAmHkdvQxjyOnbNALbuv4BFw/Wwj3pQc1v4LP03GIw54jgB6Xa+VZLfWPkeqG7PkN2o cIrELfbuB/fiI2Bwr2Z6NWZCgWNKU+5jt3N097TRjP5zefz/lHiYzm24Mz/FqzeHQ5DL T6GA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=wTHIF3kzHwKHxz6sbdTA6HigpvBZ0MJTrxRLydloFco=; b=Zu5wxEmRdp2ZPu2oj+u1l/S+PQ+InIQr3+LWtYnWOdDWZG0oTDUlCBdtgpBSTCtPUx aI63qqhxD7E5yjOfqBiuY0Qde2nMvVghEtp9X5alYFLsJc7/V7sJjodSkDu7JcKZyBhi iMIC1PRo9FmC3M3q7i40ujwb5XDXb+B9vay1LPENVFAiVKC5ondmTSEfIjjrnIVTrO5+ 1Z/cee0WUwu1qDHfsHbxlJQZaSF9Jrarsp7DMMEFb6iqXtuzbchM3q5xHY3ZCxtxpaeK Fjy52WSj7SylqWn+6F2ARnyOBwyov2oOCtcy9jYBsb4Dx27r5AgcmYFuwBgWrZwIQc1T drVw== X-Gm-Message-State: AOPr4FVZKDXWMm+Zem9I5bP3usYAqkYHhFDgkJYYuzAu/5euQBDdeafk0/uTOPelFz003Q== X-Received: by 10.28.211.10 with SMTP id k10mr6661590wmg.82.1462521023541; Fri, 06 May 2016 00:50:23 -0700 (PDT) Received: from haswell.alporthouse.com ([78.156.65.138]) by smtp.gmail.com with ESMTPSA id b15sm7054721wmd.1.2016.05.06.00.50.22 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 06 May 2016 00:50:22 -0700 (PDT) From: Chris Wilson To: intel-gfx@lists.freedesktop.org Date: Fri, 6 May 2016 08:50:14 +0100 Message-Id: <1462521014-13595-1-git-send-email-chris@chris-wilson.co.uk> X-Mailer: git-send-email 2.8.1 In-Reply-To: <1462442809-1842-1-git-send-email-kenneth@whitecape.org> References: <1462442809-1842-1-git-send-email-kenneth@whitecape.org> Cc: Kenneth Graunke Subject: [Intel-gfx] [PATCH v2] drm/i915: Allow MI_LOAD_REGISTER_REG between whitelisted registers. X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-6.2 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Kenneth Graunke Allowing register copies where the source and destination are both whitelisted should be safe, and is useful. For example, Mesa uses this to load the command streamer math registers with data from the pipeline statistics counters. v2: Reject writes to OACONTROL (and reads as well :( Signed-off-by: Kenneth Graunke Reviewed-by: Chris Wilson # v1 Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/i915_cmd_parser.c | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c index 69a1ba8ebdfb..c3a760375905 100644 --- a/drivers/gpu/drm/i915/i915_cmd_parser.c +++ b/drivers/gpu/drm/i915/i915_cmd_parser.c @@ -215,7 +215,8 @@ static const struct drm_i915_cmd_descriptor hsw_render_cmds[] = { CMD( MI_RS_CONTEXT, SMI, F, 1, S ), CMD( MI_LOAD_SCAN_LINES_INCL, SMI, !F, 0x3F, M ), CMD( MI_LOAD_SCAN_LINES_EXCL, SMI, !F, 0x3F, R ), - CMD( MI_LOAD_REGISTER_REG, SMI, !F, 0xFF, R ), + CMD( MI_LOAD_REGISTER_REG, SMI, !F, 0xFF, W, + .reg = { .offset = 1, .mask = 0x007FFFFC, .step = 1 } ), CMD( MI_RS_STORE_DATA_IMM, SMI, !F, 0xFF, S ), CMD( MI_LOAD_URB_MEM, SMI, !F, 0xFF, S ), CMD( MI_STORE_URB_MEM, SMI, !F, 0xFF, S ), @@ -1098,6 +1099,11 @@ static bool check_cmd(const struct intel_engine_cs *engine, return false; } + if (desc->cmd.value == MI_LOAD_REGISTER_REG) { + DRM_DEBUG_DRIVER("CMD: Rejected LRR to OACONTROL\n"); + return false; + } + if (desc->cmd.value == MI_LOAD_REGISTER_IMM(1)) *oacontrol_set = (cmd[offset + 1] != 0); } @@ -1113,6 +1119,12 @@ static bool check_cmd(const struct intel_engine_cs *engine, return false; } + if (desc->cmd.value == MI_LOAD_REGISTER_REG) { + DRM_DEBUG_DRIVER("CMD: Rejected LRR to masked register 0x%08X\n", + reg_addr); + return false; + } + if (desc->cmd.value == MI_LOAD_REGISTER_IMM(1) && (offset + 2 > length || (cmd[offset + 1] & reg->mask) != reg->value)) { @@ -1301,6 +1313,7 @@ int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv) * 4. L3 atomic chicken bits of HSW_SCRATCH1 and HSW_ROW_CHICKEN3. * 5. GPGPU dispatch compute indirect registers. * 6. TIMESTAMP register and Haswell CS GPR registers + * 7. Allow MI_LOAD_REGISTER_REG between whitelisted registers. */ - return 6; + return 7; }