| Message ID | 1463148903-6337-7-git-send-email-ander.conselvan.de.oliveira@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Fri, May 13, 2016 at 05:15:03PM +0300, Ander Conselvan de Oliveira wrote: > This simplifies the pll enable/disable a code a bit and hides the > sideband message neatly in intel_dpio_phy.c. > > Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> > --- > drivers/gpu/drm/i915/i915_drv.h | 2 ++ > drivers/gpu/drm/i915/intel_display.c | 19 ++----------------- > drivers/gpu/drm/i915/intel_dpio_phy.c | 18 ++++++++++++++++++ > 3 files changed, 22 insertions(+), 17 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index 149317c..44f4b7a 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -3630,6 +3630,8 @@ void chv_phy_post_pll_disable(struct intel_encoder *encoder); > void chv_phy_prepare_pll(struct intel_crtc *crtc, u32 bestn, > u32 bestm1, u32 bestm2, u32 bestp1, u32 bestp2, > int vco); > +void chv_phy_toggle_dclkp(struct drm_i915_private *dev_priv, enum pipe pipe, > + bool enable); Toggle makes me think it just flips the bit. _enable_dclkp() _set_dclkp() or something might be better? > void chv_phy_read_dividers(struct drm_i915_private *dev_priv, > enum pipe pipe, struct intel_dpll *clock); > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index 5ba000a..d43bdff 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -1574,17 +1574,9 @@ static void _chv_enable_pll(struct intel_crtc *crtc, > { > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); > enum pipe pipe = crtc->pipe; > - enum dpio_channel port = vlv_pipe_to_channel(pipe); > - u32 tmp; > - > - mutex_lock(&dev_priv->sb_lock); > > /* Enable back the 10bit clock to display controller */ > - tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); > - tmp |= DPIO_DCLKP_EN; > - vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp); > - > - mutex_unlock(&dev_priv->sb_lock); > + chv_phy_toggle_dclkp(dev_priv, pipe, true); > > /* > * Need to wait > 100ns between dclkp clock enable bit and PLL enable. > @@ -1777,7 +1769,6 @@ static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) > > static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) > { > - enum dpio_channel port = vlv_pipe_to_channel(pipe); > u32 val; > > /* Make sure the pipe isn't still relying on us */ > @@ -1791,14 +1782,8 @@ static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) > I915_WRITE(DPLL(pipe), val); > POSTING_READ(DPLL(pipe)); > > - mutex_lock(&dev_priv->sb_lock); > - > /* Disable 10bit clock to display controller */ > - val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); > - val &= ~DPIO_DCLKP_EN; > - vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val); > - > - mutex_unlock(&dev_priv->sb_lock); > + chv_phy_toggle_dclkp(dev_priv, pipe, false); > } > > void vlv_wait_port_ready(struct drm_i915_private *dev_priv, > diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c b/drivers/gpu/drm/i915/intel_dpio_phy.c > index 2a5d333..64788e3 100644 > --- a/drivers/gpu/drm/i915/intel_dpio_phy.c > +++ b/drivers/gpu/drm/i915/intel_dpio_phy.c > @@ -461,6 +461,24 @@ void chv_phy_prepare_pll(struct intel_crtc *crtc, u32 bestn, > mutex_unlock(&dev_priv->sb_lock); > } > > +void chv_phy_toggle_dclkp(struct drm_i915_private *dev_priv, enum pipe pipe, > + bool enable) > +{ > + enum dpio_channel port = vlv_pipe_to_channel(pipe); > + u32 dpio_val; > + > + mutex_lock(&dev_priv->sb_lock); > + > + dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); > + if (enable) > + dpio_val |= DPIO_DCLKP_EN; > + else > + dpio_val &= ~DPIO_DCLKP_EN; > + vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), dpio_val); > + > + mutex_unlock(&dev_priv->sb_lock); > +} > + > void chv_phy_read_dividers(struct drm_i915_private *dev_priv, > enum pipe pipe, struct intel_dpll *clock) > { > -- > 2.5.5 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
On Fri, 2016-05-13 at 17:25 +0300, Ville Syrjälä wrote: > On Fri, May 13, 2016 at 05:15:03PM +0300, Ander Conselvan de Oliveira wrote: > > > > This simplifies the pll enable/disable a code a bit and hides the > > sideband message neatly in intel_dpio_phy.c. > > > > Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@inte > > l.com> > > --- > > drivers/gpu/drm/i915/i915_drv.h | 2 ++ > > drivers/gpu/drm/i915/intel_display.c | 19 ++----------------- > > drivers/gpu/drm/i915/intel_dpio_phy.c | 18 ++++++++++++++++++ > > 3 files changed, 22 insertions(+), 17 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/i915_drv.h > > b/drivers/gpu/drm/i915/i915_drv.h > > index 149317c..44f4b7a 100644 > > --- a/drivers/gpu/drm/i915/i915_drv.h > > +++ b/drivers/gpu/drm/i915/i915_drv.h > > @@ -3630,6 +3630,8 @@ void chv_phy_post_pll_disable(struct intel_encoder > > *encoder); > > void chv_phy_prepare_pll(struct intel_crtc *crtc, u32 bestn, > > u32 bestm1, u32 bestm2, u32 bestp1, u32 bestp2, > > int vco); > > +void chv_phy_toggle_dclkp(struct drm_i915_private *dev_priv, enum pipe > > pipe, > > + bool enable); > Toggle makes me think it just flips the bit. _enable_dclkp() > _set_dclkp() or something might be better? I'll resend with _set. I find a bit weird to have a function called enable that disables things. Ander > > > > > void chv_phy_read_dividers(struct drm_i915_private *dev_priv, > > enum pipe pipe, struct intel_dpll *clock); > > > > diff --git a/drivers/gpu/drm/i915/intel_display.c > > b/drivers/gpu/drm/i915/intel_display.c > > index 5ba000a..d43bdff 100644 > > --- a/drivers/gpu/drm/i915/intel_display.c > > +++ b/drivers/gpu/drm/i915/intel_display.c > > @@ -1574,17 +1574,9 @@ static void _chv_enable_pll(struct intel_crtc *crtc, > > { > > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); > > enum pipe pipe = crtc->pipe; > > - enum dpio_channel port = vlv_pipe_to_channel(pipe); > > - u32 tmp; > > - > > - mutex_lock(&dev_priv->sb_lock); > > > > /* Enable back the 10bit clock to display controller */ > > - tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); > > - tmp |= DPIO_DCLKP_EN; > > - vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp); > > - > > - mutex_unlock(&dev_priv->sb_lock); > > + chv_phy_toggle_dclkp(dev_priv, pipe, true); > > > > /* > > * Need to wait > 100ns between dclkp clock enable bit and PLL > > enable. > > @@ -1777,7 +1769,6 @@ static void vlv_disable_pll(struct drm_i915_private > > *dev_priv, enum pipe pipe) > > > > static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe > > pipe) > > { > > - enum dpio_channel port = vlv_pipe_to_channel(pipe); > > u32 val; > > > > /* Make sure the pipe isn't still relying on us */ > > @@ -1791,14 +1782,8 @@ static void chv_disable_pll(struct drm_i915_private > > *dev_priv, enum pipe pipe) > > I915_WRITE(DPLL(pipe), val); > > POSTING_READ(DPLL(pipe)); > > > > - mutex_lock(&dev_priv->sb_lock); > > - > > /* Disable 10bit clock to display controller */ > > - val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); > > - val &= ~DPIO_DCLKP_EN; > > - vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val); > > - > > - mutex_unlock(&dev_priv->sb_lock); > > + chv_phy_toggle_dclkp(dev_priv, pipe, false); > > } > > > > void vlv_wait_port_ready(struct drm_i915_private *dev_priv, > > diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c > > b/drivers/gpu/drm/i915/intel_dpio_phy.c > > index 2a5d333..64788e3 100644 > > --- a/drivers/gpu/drm/i915/intel_dpio_phy.c > > +++ b/drivers/gpu/drm/i915/intel_dpio_phy.c > > @@ -461,6 +461,24 @@ void chv_phy_prepare_pll(struct intel_crtc *crtc, u32 > > bestn, > > mutex_unlock(&dev_priv->sb_lock); > > } > > > > +void chv_phy_toggle_dclkp(struct drm_i915_private *dev_priv, enum pipe > > pipe, > > + bool enable) > > +{ > > + enum dpio_channel port = vlv_pipe_to_channel(pipe); > > + u32 dpio_val; > > + > > + mutex_lock(&dev_priv->sb_lock); > > + > > + dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); > > + if (enable) > > + dpio_val |= DPIO_DCLKP_EN; > > + else > > + dpio_val &= ~DPIO_DCLKP_EN; > > + vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), dpio_val); > > + > > + mutex_unlock(&dev_priv->sb_lock); > > +} > > + > > void chv_phy_read_dividers(struct drm_i915_private *dev_priv, > > enum pipe pipe, struct intel_dpll *clock) > > { > > -- > > 2.5.5 > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 149317c..44f4b7a 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -3630,6 +3630,8 @@ void chv_phy_post_pll_disable(struct intel_encoder *encoder); void chv_phy_prepare_pll(struct intel_crtc *crtc, u32 bestn, u32 bestm1, u32 bestm2, u32 bestp1, u32 bestp2, int vco); +void chv_phy_toggle_dclkp(struct drm_i915_private *dev_priv, enum pipe pipe, + bool enable); void chv_phy_read_dividers(struct drm_i915_private *dev_priv, enum pipe pipe, struct intel_dpll *clock); diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 5ba000a..d43bdff 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -1574,17 +1574,9 @@ static void _chv_enable_pll(struct intel_crtc *crtc, { struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum pipe pipe = crtc->pipe; - enum dpio_channel port = vlv_pipe_to_channel(pipe); - u32 tmp; - - mutex_lock(&dev_priv->sb_lock); /* Enable back the 10bit clock to display controller */ - tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); - tmp |= DPIO_DCLKP_EN; - vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp); - - mutex_unlock(&dev_priv->sb_lock); + chv_phy_toggle_dclkp(dev_priv, pipe, true); /* * Need to wait > 100ns between dclkp clock enable bit and PLL enable. @@ -1777,7 +1769,6 @@ static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) { - enum dpio_channel port = vlv_pipe_to_channel(pipe); u32 val; /* Make sure the pipe isn't still relying on us */ @@ -1791,14 +1782,8 @@ static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) I915_WRITE(DPLL(pipe), val); POSTING_READ(DPLL(pipe)); - mutex_lock(&dev_priv->sb_lock); - /* Disable 10bit clock to display controller */ - val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); - val &= ~DPIO_DCLKP_EN; - vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val); - - mutex_unlock(&dev_priv->sb_lock); + chv_phy_toggle_dclkp(dev_priv, pipe, false); } void vlv_wait_port_ready(struct drm_i915_private *dev_priv, diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c b/drivers/gpu/drm/i915/intel_dpio_phy.c index 2a5d333..64788e3 100644 --- a/drivers/gpu/drm/i915/intel_dpio_phy.c +++ b/drivers/gpu/drm/i915/intel_dpio_phy.c @@ -461,6 +461,24 @@ void chv_phy_prepare_pll(struct intel_crtc *crtc, u32 bestn, mutex_unlock(&dev_priv->sb_lock); } +void chv_phy_toggle_dclkp(struct drm_i915_private *dev_priv, enum pipe pipe, + bool enable) +{ + enum dpio_channel port = vlv_pipe_to_channel(pipe); + u32 dpio_val; + + mutex_lock(&dev_priv->sb_lock); + + dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); + if (enable) + dpio_val |= DPIO_DCLKP_EN; + else + dpio_val &= ~DPIO_DCLKP_EN; + vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), dpio_val); + + mutex_unlock(&dev_priv->sb_lock); +} + void chv_phy_read_dividers(struct drm_i915_private *dev_priv, enum pipe pipe, struct intel_dpll *clock) {
This simplifies the pll enable/disable a code a bit and hides the sideband message neatly in intel_dpio_phy.c. Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 2 ++ drivers/gpu/drm/i915/intel_display.c | 19 ++----------------- drivers/gpu/drm/i915/intel_dpio_phy.c | 18 ++++++++++++++++++ 3 files changed, 22 insertions(+), 17 deletions(-)