| Message ID | 1463172100-24715-10-git-send-email-ville.syrjala@linux.intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On pe, 2016-05-13 at 23:41 +0300, ville.syrjala@linux.intel.com wrote: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Also verify the DPLL_CTRL1 register value in skl_sanitize_cdclk(), throw > out a few unneeded variables, and write the CDCLK_CTL check a bit more > legible way. > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> > --- > drivers/gpu/drm/i915/intel_display.c | 18 +++++++++++++----- > 1 file changed, 13 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index 107a7799bdde..493160682b2a 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -5789,9 +5789,7 @@ void skl_init_cdclk(struct drm_i915_private *dev_priv) > > int skl_sanitize_cdclk(struct drm_i915_private *dev_priv) > { > - uint32_t lcpll1 = I915_READ(LCPLL1_CTL); > - uint32_t cdctl = I915_READ(CDCLK_CTL); > - int freq = dev_priv->cdclk_freq; > + uint32_t cdctl, expected; > > /* > * check if the pre-os intialized the display > @@ -5802,7 +5800,14 @@ int skl_sanitize_cdclk(struct drm_i915_private *dev_priv) > goto sanitize; > > /* Is PLL enabled and locked ? */ > - if (!((lcpll1 & LCPLL_PLL_ENABLE) && (lcpll1 & LCPLL_PLL_LOCK))) > + if ((I915_READ(LCPLL1_CTL) & (LCPLL_PLL_ENABLE | LCPLL_PLL_LOCK)) != > + (LCPLL_PLL_ENABLE | LCPLL_PLL_LOCK)) > + goto sanitize; > + > + if ((I915_READ(DPLL_CTRL1) & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | > + DPLL_CTRL1_SSC(SKL_DPLL0) | > + DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) != > + DPLL_CTRL1_OVERRIDE(SKL_DPLL0)) > goto sanitize; > > /* DPLL okay; verify the cdclock > @@ -5811,7 +5816,10 @@ int skl_sanitize_cdclk(struct drm_i915_private *dev_priv) > * decimal part is programmed wrong from BIOS where pre-os does not > * enable display. Verify the same as well. > */ > - if (cdctl == ((cdctl & CDCLK_FREQ_SEL_MASK) | skl_cdclk_decimal(freq))) > + cdctl = I915_READ(CDCLK_CTL); > + expected = (cdctl & CDCLK_FREQ_SEL_MASK) | > + skl_cdclk_decimal(dev_priv->cdclk_freq); > + if (cdctl == expected) > /* All well; nothing to sanitize */ > return false; > sanitize:
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 107a7799bdde..493160682b2a 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -5789,9 +5789,7 @@ void skl_init_cdclk(struct drm_i915_private *dev_priv) int skl_sanitize_cdclk(struct drm_i915_private *dev_priv) { - uint32_t lcpll1 = I915_READ(LCPLL1_CTL); - uint32_t cdctl = I915_READ(CDCLK_CTL); - int freq = dev_priv->cdclk_freq; + uint32_t cdctl, expected; /* * check if the pre-os intialized the display @@ -5802,7 +5800,14 @@ int skl_sanitize_cdclk(struct drm_i915_private *dev_priv) goto sanitize; /* Is PLL enabled and locked ? */ - if (!((lcpll1 & LCPLL_PLL_ENABLE) && (lcpll1 & LCPLL_PLL_LOCK))) + if ((I915_READ(LCPLL1_CTL) & (LCPLL_PLL_ENABLE | LCPLL_PLL_LOCK)) != + (LCPLL_PLL_ENABLE | LCPLL_PLL_LOCK)) + goto sanitize; + + if ((I915_READ(DPLL_CTRL1) & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | + DPLL_CTRL1_SSC(SKL_DPLL0) | + DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) != + DPLL_CTRL1_OVERRIDE(SKL_DPLL0)) goto sanitize; /* DPLL okay; verify the cdclock @@ -5811,7 +5816,10 @@ int skl_sanitize_cdclk(struct drm_i915_private *dev_priv) * decimal part is programmed wrong from BIOS where pre-os does not * enable display. Verify the same as well. */ - if (cdctl == ((cdctl & CDCLK_FREQ_SEL_MASK) | skl_cdclk_decimal(freq))) + cdctl = I915_READ(CDCLK_CTL); + expected = (cdctl & CDCLK_FREQ_SEL_MASK) | + skl_cdclk_decimal(dev_priv->cdclk_freq); + if (cdctl == expected) /* All well; nothing to sanitize */ return false; sanitize: