From patchwork Fri May 13 20:41:35 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ville Syrjala X-Patchwork-Id: 9093381 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id F09879F1C1 for ; Fri, 13 May 2016 20:42:38 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 16C562022D for ; Fri, 13 May 2016 20:42:38 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 31B92201F2 for ; Fri, 13 May 2016 20:42:37 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id AFFF66EB06; Fri, 13 May 2016 20:42:36 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTP id 855856EB06 for ; Fri, 13 May 2016 20:42:34 +0000 (UTC) Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga103.fm.intel.com with ESMTP; 13 May 2016 13:42:34 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.24,615,1455004800"; d="scan'208";a="702441565" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.174]) by FMSMGA003.fm.intel.com with SMTP; 13 May 2016 13:42:32 -0700 Received: by stinkbox (sSMTP sendmail emulation); Fri, 13 May 2016 23:42:31 +0300 From: ville.syrjala@linux.intel.com To: intel-gfx@lists.freedesktop.org Date: Fri, 13 May 2016 23:41:35 +0300 Message-Id: <1463172100-24715-17-git-send-email-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1463172100-24715-1-git-send-email-ville.syrjala@linux.intel.com> References: <1463172100-24715-1-git-send-email-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 16/21] drm/i915: Store BXT DE PLL vco and ref clocks in dev_priv X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-5.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Ville Syrjälä We have need to know the DE PLL refclk and output frequency in various cdclk calculations, so let's store those in dev_priv. Signed-off-by: Ville Syrjälä Reviewed-by: Imre Deak --- drivers/gpu/drm/i915/intel_display.c | 27 ++++++++++++++++++++++++++- 1 file changed, 26 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 76d59d1214f4..0d55e8175573 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -5334,7 +5334,7 @@ static void intel_update_cdclk(struct drm_device *dev) dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev); - if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) + if (INTEL_GEN(dev_priv) >= 9) DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz, VCO: %d kHz, ref: %d kHz\n", dev_priv->cdclk_freq, dev_priv->cdclk_pll.vco, dev_priv->cdclk_pll.ref); @@ -5365,6 +5365,8 @@ static void bxt_de_pll_disable(struct drm_i915_private *dev_priv) /* Timeout 200us */ if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) == 0, 1)) DRM_ERROR("timeout waiting for DE PLL unlock\n"); + + dev_priv->cdclk_pll.vco = 0; } static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, u32 ratio) @@ -5381,6 +5383,8 @@ static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, u32 ratio) /* Timeout 200us */ if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) != 0, 1)) DRM_ERROR("timeout waiting for DE PLL lock\n"); + + dev_priv->cdclk_pll.vco = ratio * dev_priv->cdclk_pll.ref; } static void broxton_set_cdclk(struct drm_i915_private *dev_priv, int cdclk) @@ -6697,6 +6701,25 @@ static int skylake_get_display_clock_speed(struct drm_device *dev) return dev_priv->cdclk_pll.ref; } +static void bxt_de_pll_update(struct drm_i915_private *dev_priv) +{ + u32 val; + + dev_priv->cdclk_pll.ref = 19200; + + val = I915_READ(BXT_DE_PLL_ENABLE); + if ((val & BXT_DE_PLL_PLL_ENABLE) == 0) { + dev_priv->cdclk_pll.vco = 0; + return; + } + + WARN_ON((val & BXT_DE_PLL_LOCK) == 0); + + val = I915_READ(BXT_DE_PLL_CTL); + dev_priv->cdclk_pll.vco = (val & BXT_DE_PLL_RATIO_MASK) * + dev_priv->cdclk_pll.ref; +} + static int broxton_get_display_clock_speed(struct drm_device *dev) { struct drm_i915_private *dev_priv = to_i915(dev); @@ -6705,6 +6728,8 @@ static int broxton_get_display_clock_speed(struct drm_device *dev) uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE); int cdclk; + bxt_de_pll_update(dev_priv); + if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE)) return 19200;