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[v2,4/7] drm: Read DPCD receiver capability for DP to HDMI converter

Message ID 1463404773-5167-5-git-send-email-mika.kahola@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Mika Kahola May 16, 2016, 1:19 p.m. UTC 
Read from DPCD receiver capability field for DP to HDMI
converter. The features for DP to HDMI converter are

 - max TMDS characther clock rate
 - max bits per component
 - support for conversion from 3D frame sequential to frame pack
 - support for YCBCR422 pass through
 - support for YCBCR420 pass through
 - support for conversion from YCBCR444 to YCBCR422
 - support for conversion from YCBCR444 to YCBCR420

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/drm_dp_helper.c |  8 ++++++++
 include/drm/drm_dp_helper.h     | 19 +++++++++++++++++++
 2 files changed, 27 insertions(+)
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Patch

diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index f5cf706..ccd0fcb 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -456,6 +456,14 @@  int drm_dp_bd(struct drm_dp_aux *aux, struct drm_dp_bd *bd)
 			bd->dfp.dvi.bpc = info[2] & DP_DS_VGA_MAX_BPC_MASK;
 			bd->dfp.dvi.dual_link = info[3] & DP_DS_DVI_DUAL_LINK;
 			bd->dfp.dvi.hi_color_depth = info[3] & DP_DS_DVI_HI_COLOR_DEPTH;
+		} else if (bd->type & DP_DS_PORT_TYPE_HDMI) {
+			bd->dfp.hdmi.tmds_clk = info[1] * 2500;
+			bd->dfp.hdmi.bpc = info[2] & DP_DS_VGA_MAX_BPC_MASK;
+			bd->dfp.hdmi.frame_seq_to_frame_pack = info[3] & FRAME_SEQ_TO_FRAME_PACK;
+			bd->dfp.hdmi.ycbcr422_pass_through = info[3] & YCBCR422_PASS_THROUGH;
+			bd->dfp.hdmi.ycbcr420_pass_through = info[3] & YCBCR420_PASS_THROUGH;
+			bd->dfp.hdmi.conversion_from_ycbcr444_to_ycbcr422 = info[3] & YCBCR444_TO_YCBCR422;
+			bd->dfp.hdmi.conversion_from_ycbcr444_to_ycbcr420 = info[3] & YCBCR444_TO_YCBCR420;
 		}
 	}
 
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index da82459..3607250 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -223,6 +223,12 @@ 
 /* offset 3 for DVI dual link and high color depth */
 # define DP_DS_DVI_DUAL_LINK                (1<<1)
 # define DP_DS_DVI_HI_COLOR_DEPTH           (1<<2)
+/* offset 3 for HDMI */
+# define FRAME_SEQ_TO_FRAME_PACK            (1<<0)
+# define YCBCR422_PASS_THROUGH              (1<<1)
+# define YCBCR420_PASS_THROUGH              (1<<2)
+# define YCBCR444_TO_YCBCR422               (1<<3)
+# define YCBCR444_TO_YCBCR420               (1<<4)
 
 /* link configuration */
 #define	DP_LINK_BW_SET		            0x100
@@ -821,6 +827,18 @@  struct drm_dp_dvi {
 	bool dual_link;
 	bool hi_color_depth;
 };
+/*
+ * DP to HDMI
+ */
+struct drm_dp_hdmi {
+	int tmds_clk;
+	uint8_t bpc;
+	bool frame_seq_to_frame_pack;
+	bool ycbcr422_pass_through;
+	bool ycbcr420_pass_through;
+	bool conversion_from_ycbcr444_to_ycbcr422;
+	bool conversion_from_ycbcr444_to_ycbcr420;
+};
 
 /*
  * Branch device
@@ -832,6 +850,7 @@  struct drm_dp_bd {
 	union {
 		struct drm_dp_vga vga;
 		struct drm_dp_dvi dvi;
+		struct drm_dp_hdmi hdmi;
 	} dfp;
 };