From patchwork Tue May 17 08:19:09 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Wang, Zhi A" X-Patchwork-Id: 9110481 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id C6E3F9F1C1 for ; Tue, 17 May 2016 08:20:17 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id E7447201ED for ; Tue, 17 May 2016 08:20:16 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id F2BBA201B4 for ; Tue, 17 May 2016 08:20:15 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 40EAC6E64E; Tue, 17 May 2016 08:20:15 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTP id 8B9D46E64A for ; Tue, 17 May 2016 08:19:39 +0000 (UTC) Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga102.fm.intel.com with ESMTP; 17 May 2016 01:19:40 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.26,324,1459839600"; d="scan'208";a="105209130" Received: from zhiwang1-mobl4.ccr.corp.intel.com (HELO inno-VirtualBox.fi.intel.com) ([10.237.66.154]) by fmsmga004.fm.intel.com with ESMTP; 17 May 2016 01:19:34 -0700 From: Zhi Wang To: intel-gfx@lists.freedesktop.org, tvrtko.ursulin@linux.intel.com, joonas.lahtinen@linux.intel.com, chris@chris-wilson.co.uk, kevin.tian@intel.com, zhiyuan.lv@intel.com Date: Tue, 17 May 2016 04:19:09 -0400 Message-Id: <1463473149-5876-10-git-send-email-zhi.a.wang@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1463473149-5876-1-git-send-email-zhi.a.wang@intel.com> References: <1463473149-5876-1-git-send-email-zhi.a.wang@intel.com> Subject: [Intel-gfx] [PATCH 9/9] drm/i915: Introduce GVT context creation API X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-5.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP GVT workload scheduler needs special host LRC contexts, the so called "shadow LRC context" to submit guest workload to host i915. During the guest workload submission, GVT fills the shadow LRC context with the content of guest LRC context: engine context is copied without changes, ring context is mostly owned by host i915. The GVT-g workload scheduler flow: +-----------+ +-----------+ | GVT Guest | | GVT Guest | +-+-----^---+ +-+-----^---+ | | | | | | GVT-g | | GVT-g vELSP write| | emulates vELSP write| | emulates | | Execlist/CSB | | Execlist/CSB | | Status | | Status | | | | +------v-----+-------------------------v-----+---------+ | GVT Virtual Execlist Submission | +------+-------------------------------+---------------+ | | | Per-VM/Ring Workoad Q | Per-VM/Ring Workload Q +---------------------+--+ +------------------------+ +---v--------+ ^ +---v--------+ |GVT Workload|... | |GVT Workload|... +------------+ | +------------+ | | Pick Workload from Q +--------------------+---------------------------------+ | GVT Workload Scheduler | +--------------------+---------------------------------+ | * Shadow guest LRC context +------v------+ * Shadow guest ring buffer | GVT Context | * Scan/Patch guest RB instructions +------+------+ | v Host i915 GEM Submission v5: - Only compile this feature when CONFIG_DRM_I915_GVT is enabled. - Rebase the code into new repo. - Add a comment about the ring buffer size. v2: Mostly based on Daniel's idea. Call the refactored core logic of GEM context creation service and LRC context creation service to create the GVT context. Signed-off-by: Zhi Wang --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_gem_context.c | 31 +++++++++++++++++++++++++++++++ 2 files changed, 32 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index b8f1e9a..7e5a506 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -3398,6 +3398,7 @@ i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id); void i915_gem_context_free(struct kref *ctx_ref); struct drm_i915_gem_object * i915_gem_alloc_context_obj(struct drm_device *dev, size_t size); +struct intel_context *i915_gem_create_gvt_context(struct drm_device *dev); static inline void i915_gem_context_reference(struct intel_context *ctx) { kref_get(&ctx->ref); diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c index 057e2fe..a69bb86 100644 --- a/drivers/gpu/drm/i915/i915_gem_context.c +++ b/drivers/gpu/drm/i915/i915_gem_context.c @@ -354,6 +354,37 @@ err_destroy: return ERR_PTR(ret); } +#if IS_ENABLED(CONFIG_DRM_I915_GVT) +/** + * i915_gem_create_gvt_context - create a GVT GEM context + * @dev: drm device * + * + * This function is used to create a GVT specific GEM context. + * + * Returns: + * pointer to intel_context on success, NULL if failed + * + */ +struct intel_context * +i915_gem_create_gvt_context(struct drm_device *dev) +{ + struct intel_context *ctx; + + mutex_lock(&dev->struct_mutex); + + ctx = i915_gem_create_context(dev, NULL); + if (IS_ERR(ctx)) + goto out; + + ctx->enable_status_change_notification = true; + ctx->ring_buffer_size = 512 * PAGE_SIZE; /* Max ring buffer size */ + ctx->single_submission = true; +out: + mutex_unlock(&dev->struct_mutex); + return ctx; +} +#endif + static void i915_gem_context_unpin(struct intel_context *ctx, struct intel_engine_cs *engine) {