| Message ID | 1463473149-5876-5-git-send-email-zhi.a.wang@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Tue, May 17, 2016 at 04:19:04AM -0400, Zhi Wang wrote: > From: Bing Niu <bing.niu@intel.com> > > This patch introduces host graphics memory partition when GVT-g > is enabled. > > Under GVT-g, i915 host driver only owned limited graphics resources, > others are managed by GVT-g resource allocator and kept for other vGPUs. Strong justification required for why the user is expected to get these right via module parameters. > +/* > + * Under GVT-g, i915 host driver only owned limited graphics resources, > + * others are managed by GVT-g resource allocator and kept for other vGPUs. > + * > + * For graphics memory space partition, a typical layout looks like: > + * > + * +-------+-----------------------+------+-----------------------+ > + * |* Host | *GVT-g Resource |* Host| *GVT-g Resource | > + * | Owned | Allocator Managed | Owned| Allocator Managed | > + * | | | | | > + * +---------------+-------+----------------------+-------+-------+ > + * | | | | | | | | | > + * | i915 | vm 1 | vm 2 | vm 3 | i915 | vm 1 | vm 2 | vm 3 | > + * | | | | | | | | | > + * +-------+-------+-------+--------------+-------+-------+-------+ > + * | Aperture | Hidden | > + * +-------------------------------+------------------------------+ > + * | GGTT memory space | > + * +--------------------------------------------------------------+ > + */ > struct i915_gvt { > void *gvt; > + u64 low_gm_size; > + u64 high_gm_size; > }; > > struct i915_virtual_gpu { > diff --git a/drivers/gpu/drm/i915/i915_vgpu.c b/drivers/gpu/drm/i915/i915_vgpu.c > index 5312816..9382f04 100644 > --- a/drivers/gpu/drm/i915/i915_vgpu.c > +++ b/drivers/gpu/drm/i915/i915_vgpu.c > @@ -189,13 +189,24 @@ int intel_vgt_balloon(struct drm_i915_private *dev_priv) > unsigned long unmappable_base, unmappable_size, unmappable_end; > int ret; > > - if (!intel_vgpu_active(dev_priv)) > + if (!intel_vgpu_active(dev_priv) && !intel_gvt_active(dev_priv)) > return 0; > > - mappable_base = I915_READ(vgtif_reg(avail_rs.mappable_gmadr.base)); > - mappable_size = I915_READ(vgtif_reg(avail_rs.mappable_gmadr.size)); > - unmappable_base = I915_READ(vgtif_reg(avail_rs.nonmappable_gmadr.base)); > - unmappable_size = I915_READ(vgtif_reg(avail_rs.nonmappable_gmadr.size)); > + if (intel_gvt_active(dev_priv)) { > + mappable_base = 0; > + mappable_size = dev_priv->gvt.low_gm_size; > + unmappable_base = dev_priv->ggtt.mappable_end; > + unmappable_size = dev_priv->gvt.high_gm_size; > + } else if (intel_vgpu_active(dev_priv)) { > + mappable_base = I915_READ( > + vgtif_reg(avail_rs.mappable_gmadr.base)); > + mappable_size = I915_READ( > + vgtif_reg(avail_rs.mappable_gmadr.size)); > + unmappable_base = I915_READ( > + vgtif_reg(avail_rs.nonmappable_gmadr.base)); > + unmappable_size = I915_READ( > + vgtif_reg(avail_rs.nonmappable_gmadr.size)); > + } else return 0; and lose the early return. -Chris
> -----Original Message----- > From: Chris Wilson [mailto:chris@chris-wilson.co.uk] > Sent: Friday, May 20, 2016 3:01 PM > To: Wang, Zhi A <zhi.a.wang@intel.com> > Cc: intel-gfx@lists.freedesktop.org; tvrtko.ursulin@linux.intel.com; > joonas.lahtinen@linux.intel.com; Tian, Kevin <kevin.tian@intel.com>; Lv, > Zhiyuan <zhiyuan.lv@intel.com>; Niu, Bing <bing.niu@intel.com> > Subject: Re: [PATCH 4/9] drm/i915: Introduce host graphics memory partition > for GVT-g > > On Tue, May 17, 2016 at 04:19:04AM -0400, Zhi Wang wrote: > > From: Bing Niu <bing.niu@intel.com> > > > > This patch introduces host graphics memory partition when GVT-g is > > enabled. > > > > Under GVT-g, i915 host driver only owned limited graphics resources, > > others are managed by GVT-g resource allocator and kept for other vGPUs. > > Strong justification required for why the user is expected to get these right via > module parameters. > Sure, will add more comments in both code and patches about that. > > +/* > > + * Under GVT-g, i915 host driver only owned limited graphics > > +resources, > > + * others are managed by GVT-g resource allocator and kept for other > vGPUs. > > + * > > + * For graphics memory space partition, a typical layout looks like: > > + * > > + * +-------+-----------------------+------+-----------------------+ > > + * |* Host | *GVT-g Resource |* Host| *GVT-g Resource | > > + * | Owned | Allocator Managed | Owned| Allocator Managed | > > + * | | | | > | > > + * +---------------+-------+----------------------+-------+-------+ > > + * | | | | | | | | > | > > + * | i915 | vm 1 | vm 2 | vm 3 | i915 | vm 1 | vm 2 | vm 3 | > > + * | | | | | | | | > | > > + * +-------+-------+-------+--------------+-------+-------+-------+ > > + * | Aperture | Hidden > | > > + * +-------------------------------+------------------------------+ > > + * | GGTT memory space > | > > + * +--------------------------------------------------------------+ > > + */ > > struct i915_gvt { > > void *gvt; > > + u64 low_gm_size; > > + u64 high_gm_size; > > }; > > > > struct i915_virtual_gpu { > > diff --git a/drivers/gpu/drm/i915/i915_vgpu.c > > b/drivers/gpu/drm/i915/i915_vgpu.c > > index 5312816..9382f04 100644 > > --- a/drivers/gpu/drm/i915/i915_vgpu.c > > +++ b/drivers/gpu/drm/i915/i915_vgpu.c > > @@ -189,13 +189,24 @@ int intel_vgt_balloon(struct drm_i915_private > *dev_priv) > > unsigned long unmappable_base, unmappable_size, unmappable_end; > > int ret; > > > > - if (!intel_vgpu_active(dev_priv)) > > + if (!intel_vgpu_active(dev_priv) && !intel_gvt_active(dev_priv)) > > return 0; > > > > - mappable_base = I915_READ(vgtif_reg(avail_rs.mappable_gmadr.base)); > > - mappable_size = I915_READ(vgtif_reg(avail_rs.mappable_gmadr.size)); > > - unmappable_base = > I915_READ(vgtif_reg(avail_rs.nonmappable_gmadr.base)); > > - unmappable_size = > I915_READ(vgtif_reg(avail_rs.nonmappable_gmadr.size)); > > + if (intel_gvt_active(dev_priv)) { > > + mappable_base = 0; > > + mappable_size = dev_priv->gvt.low_gm_size; > > + unmappable_base = dev_priv->ggtt.mappable_end; > > + unmappable_size = dev_priv->gvt.high_gm_size; > > + } else if (intel_vgpu_active(dev_priv)) { > > + mappable_base = I915_READ( > > + vgtif_reg(avail_rs.mappable_gmadr.base)); > > + mappable_size = I915_READ( > > + vgtif_reg(avail_rs.mappable_gmadr.size)); > > + unmappable_base = I915_READ( > > + vgtif_reg(avail_rs.nonmappable_gmadr.base)); > > + unmappable_size = I915_READ( > > + vgtif_reg(avail_rs.nonmappable_gmadr.size)); > > + } > else > return 0; > > and lose the early return. OK. > -Chris > > -- > Chris Wilson, Intel Open Source Technology Centre
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 7d0b8d3..ea04352 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1703,8 +1703,30 @@ struct i915_workarounds { u32 hw_whitelist_count[I915_NUM_ENGINES]; }; +/* + * Under GVT-g, i915 host driver only owned limited graphics resources, + * others are managed by GVT-g resource allocator and kept for other vGPUs. + * + * For graphics memory space partition, a typical layout looks like: + * + * +-------+-----------------------+------+-----------------------+ + * |* Host | *GVT-g Resource |* Host| *GVT-g Resource | + * | Owned | Allocator Managed | Owned| Allocator Managed | + * | | | | | + * +---------------+-------+----------------------+-------+-------+ + * | | | | | | | | | + * | i915 | vm 1 | vm 2 | vm 3 | i915 | vm 1 | vm 2 | vm 3 | + * | | | | | | | | | + * +-------+-------+-------+--------------+-------+-------+-------+ + * | Aperture | Hidden | + * +-------------------------------+------------------------------+ + * | GGTT memory space | + * +--------------------------------------------------------------+ + */ struct i915_gvt { void *gvt; + u64 low_gm_size; + u64 high_gm_size; }; struct i915_virtual_gpu { diff --git a/drivers/gpu/drm/i915/i915_vgpu.c b/drivers/gpu/drm/i915/i915_vgpu.c index 5312816..9382f04 100644 --- a/drivers/gpu/drm/i915/i915_vgpu.c +++ b/drivers/gpu/drm/i915/i915_vgpu.c @@ -189,13 +189,24 @@ int intel_vgt_balloon(struct drm_i915_private *dev_priv) unsigned long unmappable_base, unmappable_size, unmappable_end; int ret; - if (!intel_vgpu_active(dev_priv)) + if (!intel_vgpu_active(dev_priv) && !intel_gvt_active(dev_priv)) return 0; - mappable_base = I915_READ(vgtif_reg(avail_rs.mappable_gmadr.base)); - mappable_size = I915_READ(vgtif_reg(avail_rs.mappable_gmadr.size)); - unmappable_base = I915_READ(vgtif_reg(avail_rs.nonmappable_gmadr.base)); - unmappable_size = I915_READ(vgtif_reg(avail_rs.nonmappable_gmadr.size)); + if (intel_gvt_active(dev_priv)) { + mappable_base = 0; + mappable_size = dev_priv->gvt.low_gm_size; + unmappable_base = dev_priv->ggtt.mappable_end; + unmappable_size = dev_priv->gvt.high_gm_size; + } else if (intel_vgpu_active(dev_priv)) { + mappable_base = I915_READ( + vgtif_reg(avail_rs.mappable_gmadr.base)); + mappable_size = I915_READ( + vgtif_reg(avail_rs.mappable_gmadr.size)); + unmappable_base = I915_READ( + vgtif_reg(avail_rs.nonmappable_gmadr.base)); + unmappable_size = I915_READ( + vgtif_reg(avail_rs.nonmappable_gmadr.size)); + } mappable_end = mappable_base + mappable_size; unmappable_end = unmappable_base + unmappable_size; diff --git a/drivers/gpu/drm/i915/intel_gvt.c b/drivers/gpu/drm/i915/intel_gvt.c index 815cc9f..005f156 100644 --- a/drivers/gpu/drm/i915/intel_gvt.c +++ b/drivers/gpu/drm/i915/intel_gvt.c @@ -43,6 +43,46 @@ struct gvt_kernel_params gvt_kparams = { module_param_named(gvt_enable, gvt_kparams.enable, bool, 0600); MODULE_PARM_DESC(gvt_enable, "Enable Intel GVT-g host support"); +/* i915.gvt_low_gm_size */ +module_param_named(gvt_low_gm_size, gvt_kparams.low_gm_size, charp, 0600); +MODULE_PARM_DESC(gvt_low_gm_size, "GVT low graphics memory size"); + +/* i915.gvt_high_gm_size */ +module_param_named(gvt_high_gm_size, gvt_kparams.high_gm_size, charp, 0600); +MODULE_PARM_DESC(gvt_high_gm_size, "GVT high graphics memory size"); + +#define KB(x) ((x) * 1024) +#define MB(x) (KB(x) * 1024) + +#define MAX_GVT_LOW_GM_SIZE MB(96) +#define MAX_GVT_HIGH_GM_SIZE MB(384) + +static void sanitize_gm_size(struct drm_i915_private *dev_priv) +{ + u64 low_gm_size, high_gm_size; + + low_gm_size = high_gm_size = 0; + + /* Try to parse kernel parameter first */ + if (gvt_kparams.low_gm_size) + low_gm_size = memparse(gvt_kparams.low_gm_size, NULL); + + if (gvt_kparams.high_gm_size) + high_gm_size = memparse(gvt_kparams.high_gm_size, NULL); + + if (!low_gm_size || low_gm_size > MAX_GVT_LOW_GM_SIZE) + low_gm_size = MAX_GVT_LOW_GM_SIZE; + + if (!high_gm_size || high_gm_size > MAX_GVT_HIGH_GM_SIZE) + high_gm_size = MAX_GVT_HIGH_GM_SIZE; + + dev_priv->gvt.low_gm_size = low_gm_size; + dev_priv->gvt.high_gm_size = high_gm_size; + + DRM_DEBUG_DRIVER("GVT low graphics memory size: %llx\n", low_gm_size); + DRM_DEBUG_DRIVER("GVT high graphics memory size: %llx\n", high_gm_size); +} + static bool is_supported_device(struct drm_i915_private *dev_priv) { if (IS_BROADWELL(dev_priv)) @@ -71,6 +111,8 @@ int intel_gvt_init(struct drm_i915_private *dev_priv) return 0; } + sanitize_gm_size(dev_priv); + device = intel_gvt_create_device(dev_priv); if (IS_ERR(device)) { DRM_DEBUG_DRIVER("GVT-g is disabled\n"); diff --git a/drivers/gpu/drm/i915/intel_gvt.h b/drivers/gpu/drm/i915/intel_gvt.h index 8079dfd..bfceee1 100644 --- a/drivers/gpu/drm/i915/intel_gvt.h +++ b/drivers/gpu/drm/i915/intel_gvt.h @@ -30,6 +30,8 @@ struct gvt_kernel_params { bool enable; + char *low_gm_size; + char *high_gm_size; }; extern struct gvt_kernel_params gvt_kparams;