From patchwork Tue May 17 08:19:04 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Wang, Zhi A" X-Patchwork-Id: 9110441 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 1031EBF29F for ; Tue, 17 May 2016 08:19:45 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 0D43B201CD for ; Tue, 17 May 2016 08:19:43 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id C08852010E for ; Tue, 17 May 2016 08:19:41 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id CC8906E64B; Tue, 17 May 2016 08:19:40 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id E59E66E64E for ; Tue, 17 May 2016 08:19:24 +0000 (UTC) Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga102.jf.intel.com with ESMTP; 17 May 2016 01:19:24 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.26,324,1459839600"; d="scan'208";a="105209048" Received: from zhiwang1-mobl4.ccr.corp.intel.com (HELO inno-VirtualBox.fi.intel.com) ([10.237.66.154]) by fmsmga004.fm.intel.com with ESMTP; 17 May 2016 01:19:23 -0700 From: Zhi Wang To: intel-gfx@lists.freedesktop.org, tvrtko.ursulin@linux.intel.com, joonas.lahtinen@linux.intel.com, chris@chris-wilson.co.uk, kevin.tian@intel.com, zhiyuan.lv@intel.com Date: Tue, 17 May 2016 04:19:04 -0400 Message-Id: <1463473149-5876-5-git-send-email-zhi.a.wang@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1463473149-5876-1-git-send-email-zhi.a.wang@intel.com> References: <1463473149-5876-1-git-send-email-zhi.a.wang@intel.com> Subject: [Intel-gfx] [PATCH 4/9] drm/i915: Introduce host graphics memory partition for GVT-g X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-5.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Bing Niu This patch introduces host graphics memory partition when GVT-g is enabled. Under GVT-g, i915 host driver only owned limited graphics resources, others are managed by GVT-g resource allocator and kept for other vGPUs. v3: - Remove fence partition, will use i915 fence stealing in future.(Kevin) - Santinize GVT host gm kernel parameters. (Joonas) v2: - Address all coding-style comments from Joonas previously. - Fix errors and warnning reported by checkpatch.pl. (Joonas) - Move the graphs into the header files. (Daniel) Signed-off-by: Bing Niu Signed-off-by: Zhi Wang --- drivers/gpu/drm/i915/i915_drv.h | 22 +++++++++++++++++++++ drivers/gpu/drm/i915/i915_vgpu.c | 21 +++++++++++++++----- drivers/gpu/drm/i915/intel_gvt.c | 42 ++++++++++++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_gvt.h | 2 ++ 4 files changed, 82 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 7d0b8d3..ea04352 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1703,8 +1703,30 @@ struct i915_workarounds { u32 hw_whitelist_count[I915_NUM_ENGINES]; }; +/* + * Under GVT-g, i915 host driver only owned limited graphics resources, + * others are managed by GVT-g resource allocator and kept for other vGPUs. + * + * For graphics memory space partition, a typical layout looks like: + * + * +-------+-----------------------+------+-----------------------+ + * |* Host | *GVT-g Resource |* Host| *GVT-g Resource | + * | Owned | Allocator Managed | Owned| Allocator Managed | + * | | | | | + * +---------------+-------+----------------------+-------+-------+ + * | | | | | | | | | + * | i915 | vm 1 | vm 2 | vm 3 | i915 | vm 1 | vm 2 | vm 3 | + * | | | | | | | | | + * +-------+-------+-------+--------------+-------+-------+-------+ + * | Aperture | Hidden | + * +-------------------------------+------------------------------+ + * | GGTT memory space | + * +--------------------------------------------------------------+ + */ struct i915_gvt { void *gvt; + u64 low_gm_size; + u64 high_gm_size; }; struct i915_virtual_gpu { diff --git a/drivers/gpu/drm/i915/i915_vgpu.c b/drivers/gpu/drm/i915/i915_vgpu.c index 5312816..9382f04 100644 --- a/drivers/gpu/drm/i915/i915_vgpu.c +++ b/drivers/gpu/drm/i915/i915_vgpu.c @@ -189,13 +189,24 @@ int intel_vgt_balloon(struct drm_i915_private *dev_priv) unsigned long unmappable_base, unmappable_size, unmappable_end; int ret; - if (!intel_vgpu_active(dev_priv)) + if (!intel_vgpu_active(dev_priv) && !intel_gvt_active(dev_priv)) return 0; - mappable_base = I915_READ(vgtif_reg(avail_rs.mappable_gmadr.base)); - mappable_size = I915_READ(vgtif_reg(avail_rs.mappable_gmadr.size)); - unmappable_base = I915_READ(vgtif_reg(avail_rs.nonmappable_gmadr.base)); - unmappable_size = I915_READ(vgtif_reg(avail_rs.nonmappable_gmadr.size)); + if (intel_gvt_active(dev_priv)) { + mappable_base = 0; + mappable_size = dev_priv->gvt.low_gm_size; + unmappable_base = dev_priv->ggtt.mappable_end; + unmappable_size = dev_priv->gvt.high_gm_size; + } else if (intel_vgpu_active(dev_priv)) { + mappable_base = I915_READ( + vgtif_reg(avail_rs.mappable_gmadr.base)); + mappable_size = I915_READ( + vgtif_reg(avail_rs.mappable_gmadr.size)); + unmappable_base = I915_READ( + vgtif_reg(avail_rs.nonmappable_gmadr.base)); + unmappable_size = I915_READ( + vgtif_reg(avail_rs.nonmappable_gmadr.size)); + } mappable_end = mappable_base + mappable_size; unmappable_end = unmappable_base + unmappable_size; diff --git a/drivers/gpu/drm/i915/intel_gvt.c b/drivers/gpu/drm/i915/intel_gvt.c index 815cc9f..005f156 100644 --- a/drivers/gpu/drm/i915/intel_gvt.c +++ b/drivers/gpu/drm/i915/intel_gvt.c @@ -43,6 +43,46 @@ struct gvt_kernel_params gvt_kparams = { module_param_named(gvt_enable, gvt_kparams.enable, bool, 0600); MODULE_PARM_DESC(gvt_enable, "Enable Intel GVT-g host support"); +/* i915.gvt_low_gm_size */ +module_param_named(gvt_low_gm_size, gvt_kparams.low_gm_size, charp, 0600); +MODULE_PARM_DESC(gvt_low_gm_size, "GVT low graphics memory size"); + +/* i915.gvt_high_gm_size */ +module_param_named(gvt_high_gm_size, gvt_kparams.high_gm_size, charp, 0600); +MODULE_PARM_DESC(gvt_high_gm_size, "GVT high graphics memory size"); + +#define KB(x) ((x) * 1024) +#define MB(x) (KB(x) * 1024) + +#define MAX_GVT_LOW_GM_SIZE MB(96) +#define MAX_GVT_HIGH_GM_SIZE MB(384) + +static void sanitize_gm_size(struct drm_i915_private *dev_priv) +{ + u64 low_gm_size, high_gm_size; + + low_gm_size = high_gm_size = 0; + + /* Try to parse kernel parameter first */ + if (gvt_kparams.low_gm_size) + low_gm_size = memparse(gvt_kparams.low_gm_size, NULL); + + if (gvt_kparams.high_gm_size) + high_gm_size = memparse(gvt_kparams.high_gm_size, NULL); + + if (!low_gm_size || low_gm_size > MAX_GVT_LOW_GM_SIZE) + low_gm_size = MAX_GVT_LOW_GM_SIZE; + + if (!high_gm_size || high_gm_size > MAX_GVT_HIGH_GM_SIZE) + high_gm_size = MAX_GVT_HIGH_GM_SIZE; + + dev_priv->gvt.low_gm_size = low_gm_size; + dev_priv->gvt.high_gm_size = high_gm_size; + + DRM_DEBUG_DRIVER("GVT low graphics memory size: %llx\n", low_gm_size); + DRM_DEBUG_DRIVER("GVT high graphics memory size: %llx\n", high_gm_size); +} + static bool is_supported_device(struct drm_i915_private *dev_priv) { if (IS_BROADWELL(dev_priv)) @@ -71,6 +111,8 @@ int intel_gvt_init(struct drm_i915_private *dev_priv) return 0; } + sanitize_gm_size(dev_priv); + device = intel_gvt_create_device(dev_priv); if (IS_ERR(device)) { DRM_DEBUG_DRIVER("GVT-g is disabled\n"); diff --git a/drivers/gpu/drm/i915/intel_gvt.h b/drivers/gpu/drm/i915/intel_gvt.h index 8079dfd..bfceee1 100644 --- a/drivers/gpu/drm/i915/intel_gvt.h +++ b/drivers/gpu/drm/i915/intel_gvt.h @@ -30,6 +30,8 @@ struct gvt_kernel_params { bool enable; + char *low_gm_size; + char *high_gm_size; }; extern struct gvt_kernel_params gvt_kparams;