From patchwork Tue May 17 08:32:22 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ander Conselvan de Oliveira X-Patchwork-Id: 9110611 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id A91E2BF29F for ; Tue, 17 May 2016 08:32:59 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 0352A202DD for ; Tue, 17 May 2016 08:32:55 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id E346420320 for ; Tue, 17 May 2016 08:32:53 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5C52C6E662; Tue, 17 May 2016 08:32:52 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTP id 746AD6E65D for ; Tue, 17 May 2016 08:32:38 +0000 (UTC) Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga101.fm.intel.com with ESMTP; 17 May 2016 01:32:38 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.26,324,1459839600"; d="scan'208";a="704287709" Received: from linux.intel.com ([10.23.219.25]) by FMSMGA003.fm.intel.com with ESMTP; 17 May 2016 01:32:37 -0700 Received: from localhost (aconselv-mobl3.ger.corp.intel.com [10.237.66.167]) by linux.intel.com (Postfix) with ESMTP id 48C6F6A4006; Tue, 17 May 2016 02:20:09 -0700 (PDT) From: Ander Conselvan de Oliveira To: intel-gfx@lists.freedesktop.org Date: Tue, 17 May 2016 11:32:22 +0300 Message-Id: <1463473942-5683-6-git-send-email-ander.conselvan.de.oliveira@intel.com> X-Mailer: git-send-email 2.5.5 In-Reply-To: <1463473942-5683-1-git-send-email-ander.conselvan.de.oliveira@intel.com> References: <1463473942-5683-1-git-send-email-ander.conselvan.de.oliveira@intel.com> Cc: Ander Conselvan de Oliveira Subject: [Intel-gfx] [PATCH v2 5/5] drm/i915: Move toggling of CHV DPIO_DCLKP_EN to intel_dpio_phy.c X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-5.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This simplifies the pll enable/disable a code a bit and hides the sideband message neatly in intel_dpio_phy.c. v2: Rename chv_phy_toggle_dclkp() to chv_phy_set_dclkp(). (Ville) Signed-off-by: Ander Conselvan de Oliveira --- drivers/gpu/drm/i915/i915_drv.h | 2 ++ drivers/gpu/drm/i915/intel_display.c | 19 ++----------------- drivers/gpu/drm/i915/intel_dpio_phy.c | 18 ++++++++++++++++++ 3 files changed, 22 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 894830b..36ffad6 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -3647,6 +3647,8 @@ void chv_phy_post_pll_disable(struct intel_encoder *encoder); void chv_phy_prepare_pll(struct intel_crtc *crtc, u32 bestn, u32 bestm1, u32 bestm2, u32 bestp1, u32 bestp2, int vco); +void chv_phy_set_dclkp(struct drm_i915_private *dev_priv, enum pipe pipe, + bool enable); void chv_phy_read_pll_dividers(struct drm_i915_private *dev_priv, enum pipe pipe, struct dpll *clock); diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 47cc150..64661c0 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -1575,17 +1575,9 @@ static void _chv_enable_pll(struct intel_crtc *crtc, { struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum pipe pipe = crtc->pipe; - enum dpio_channel port = vlv_pipe_to_channel(pipe); - u32 tmp; - - mutex_lock(&dev_priv->sb_lock); /* Enable back the 10bit clock to display controller */ - tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); - tmp |= DPIO_DCLKP_EN; - vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp); - - mutex_unlock(&dev_priv->sb_lock); + chv_phy_set_dclkp(dev_priv, pipe, true); /* * Need to wait > 100ns between dclkp clock enable bit and PLL enable. @@ -1778,7 +1770,6 @@ static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) { - enum dpio_channel port = vlv_pipe_to_channel(pipe); u32 val; /* Make sure the pipe isn't still relying on us */ @@ -1792,14 +1783,8 @@ static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) I915_WRITE(DPLL(pipe), val); POSTING_READ(DPLL(pipe)); - mutex_lock(&dev_priv->sb_lock); - /* Disable 10bit clock to display controller */ - val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); - val &= ~DPIO_DCLKP_EN; - vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val); - - mutex_unlock(&dev_priv->sb_lock); + chv_phy_set_dclkp(dev_priv, pipe, false); } void vlv_wait_port_ready(struct drm_i915_private *dev_priv, diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c b/drivers/gpu/drm/i915/intel_dpio_phy.c index bdd82df..9dad2d1 100644 --- a/drivers/gpu/drm/i915/intel_dpio_phy.c +++ b/drivers/gpu/drm/i915/intel_dpio_phy.c @@ -461,6 +461,24 @@ void chv_phy_prepare_pll(struct intel_crtc *crtc, u32 bestn, mutex_unlock(&dev_priv->sb_lock); } +void chv_phy_set_dclkp(struct drm_i915_private *dev_priv, enum pipe pipe, + bool enable) +{ + enum dpio_channel port = vlv_pipe_to_channel(pipe); + u32 dpio_val; + + mutex_lock(&dev_priv->sb_lock); + + dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); + if (enable) + dpio_val |= DPIO_DCLKP_EN; + else + dpio_val &= ~DPIO_DCLKP_EN; + vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), dpio_val); + + mutex_unlock(&dev_priv->sb_lock); +} + void chv_phy_read_pll_dividers(struct drm_i915_private *dev_priv, enum pipe pipe, struct dpll *clock) {