| Message ID | 1463499808-3335-2-git-send-email-mika.kuoppala@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Tue, May 17, 2016 at 06:43:22PM +0300, Mika Kuoppala wrote: > We use jiffies based resolution for timeout detection. So > the promise that in the event of timeout, we would return in the 1us > resolution is false. And with quite large margin. > > Remove the wait_for_us macro to prevent further broken promises > and convert the 3 callsites. The wait time will grow to 1ms but > this will be amended somewhat when wait_for gets enhanced with > adaptive backoff. > > Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> > --- > drivers/gpu/drm/i915/intel_ddi.c | 4 ++-- > drivers/gpu/drm/i915/intel_display.c | 8 ++++---- > drivers/gpu/drm/i915/intel_drv.h | 1 - > 3 files changed, 6 insertions(+), 7 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c > index c454744dda0b..a62c60c6fb0b 100644 > --- a/drivers/gpu/drm/i915/intel_ddi.c > +++ b/drivers/gpu/drm/i915/intel_ddi.c > @@ -1826,8 +1826,8 @@ static void broxton_phy_init(struct drm_i915_private *dev_priv, > * HW team confirmed that the time to reach phypowergood status is > * anywhere between 50 us and 100us. > */ > - if (wait_for_us(((I915_READ(BXT_PORT_CL1CM_DW0(phy)) & > - (PHY_RESERVED | PHY_POWER_GOOD)) == PHY_POWER_GOOD), 100)) { > + if (wait_for(((I915_READ(BXT_PORT_CL1CM_DW0(phy)) & > + (PHY_RESERVED | PHY_POWER_GOOD)) == PHY_POWER_GOOD), 1)) { > DRM_ERROR("timeout during PHY%d power on\n", phy); > } > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index 4777087326f6..05d4a2b365f8 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -9619,8 +9619,8 @@ static void broadwell_set_cdclk(struct drm_device *dev, int cdclk) > val |= LCPLL_CD_SOURCE_FCLK; > I915_WRITE(LCPLL_CTL, val); > > - if (wait_for_us(I915_READ(LCPLL_CTL) & > - LCPLL_CD_SOURCE_FCLK_DONE, 1)) > + if (wait_for(I915_READ(LCPLL_CTL) & > + LCPLL_CD_SOURCE_FCLK_DONE, 1)) > DRM_ERROR("Switching to FCLK failed\n"); > > val = I915_READ(LCPLL_CTL); > @@ -9654,8 +9654,8 @@ static void broadwell_set_cdclk(struct drm_device *dev, int cdclk) > val &= ~LCPLL_CD_SOURCE_FCLK; > I915_WRITE(LCPLL_CTL, val); > > - if (wait_for_us((I915_READ(LCPLL_CTL) & > - LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) > + if (wait_for((I915_READ(LCPLL_CTL) & > + LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) > DRM_ERROR("Switching back to LCPLL failed\n"); > > mutex_lock(&dev_priv->rps.hw_lock); > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h > index 3536292babe0..0fc8579e7b2e 100644 > --- a/drivers/gpu/drm/i915/intel_drv.h > +++ b/drivers/gpu/drm/i915/intel_drv.h > @@ -69,7 +69,6 @@ > }) > > #define wait_for(COND, MS) _wait_for((COND), (MS) * 1000, 1000) > -#define wait_for_us(COND, US) _wait_for((COND), (US), 1) > > /* If CONFIG_PREEMPT_COUNT is disabled, in_atomic() always reports false. */ > #if defined(CONFIG_DRM_I915_DEBUG) && defined(CONFIG_PREEMPT_COUNT) > -- > 2.5.0 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index c454744dda0b..a62c60c6fb0b 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -1826,8 +1826,8 @@ static void broxton_phy_init(struct drm_i915_private *dev_priv, * HW team confirmed that the time to reach phypowergood status is * anywhere between 50 us and 100us. */ - if (wait_for_us(((I915_READ(BXT_PORT_CL1CM_DW0(phy)) & - (PHY_RESERVED | PHY_POWER_GOOD)) == PHY_POWER_GOOD), 100)) { + if (wait_for(((I915_READ(BXT_PORT_CL1CM_DW0(phy)) & + (PHY_RESERVED | PHY_POWER_GOOD)) == PHY_POWER_GOOD), 1)) { DRM_ERROR("timeout during PHY%d power on\n", phy); } diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 4777087326f6..05d4a2b365f8 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -9619,8 +9619,8 @@ static void broadwell_set_cdclk(struct drm_device *dev, int cdclk) val |= LCPLL_CD_SOURCE_FCLK; I915_WRITE(LCPLL_CTL, val); - if (wait_for_us(I915_READ(LCPLL_CTL) & - LCPLL_CD_SOURCE_FCLK_DONE, 1)) + if (wait_for(I915_READ(LCPLL_CTL) & + LCPLL_CD_SOURCE_FCLK_DONE, 1)) DRM_ERROR("Switching to FCLK failed\n"); val = I915_READ(LCPLL_CTL); @@ -9654,8 +9654,8 @@ static void broadwell_set_cdclk(struct drm_device *dev, int cdclk) val &= ~LCPLL_CD_SOURCE_FCLK; I915_WRITE(LCPLL_CTL, val); - if (wait_for_us((I915_READ(LCPLL_CTL) & - LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) + if (wait_for((I915_READ(LCPLL_CTL) & + LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) DRM_ERROR("Switching back to LCPLL failed\n"); mutex_lock(&dev_priv->rps.hw_lock); diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 3536292babe0..0fc8579e7b2e 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -69,7 +69,6 @@ }) #define wait_for(COND, MS) _wait_for((COND), (MS) * 1000, 1000) -#define wait_for_us(COND, US) _wait_for((COND), (US), 1) /* If CONFIG_PREEMPT_COUNT is disabled, in_atomic() always reports false. */ #if defined(CONFIG_DRM_I915_DEBUG) && defined(CONFIG_PREEMPT_COUNT)
We use jiffies based resolution for timeout detection. So the promise that in the event of timeout, we would return in the 1us resolution is false. And with quite large margin. Remove the wait_for_us macro to prevent further broken promises and convert the 3 callsites. The wait time will grow to 1ms but this will be amended somewhat when wait_for gets enhanced with adaptive backoff. Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com> --- drivers/gpu/drm/i915/intel_ddi.c | 4 ++-- drivers/gpu/drm/i915/intel_display.c | 8 ++++---- drivers/gpu/drm/i915/intel_drv.h | 1 - 3 files changed, 6 insertions(+), 7 deletions(-)