From patchwork Wed May 18 16:47:12 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Daniel Vetter X-Patchwork-Id: 9121361 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 7F6D19F37F for ; Wed, 18 May 2016 16:47:37 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 89FF92034E for ; Wed, 18 May 2016 16:47:36 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id A78BD2035D for ; Wed, 18 May 2016 16:47:35 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D43CA6E899; Wed, 18 May 2016 16:47:33 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-wm0-x241.google.com (mail-wm0-x241.google.com [IPv6:2a00:1450:400c:c09::241]) by gabe.freedesktop.org (Postfix) with ESMTPS id CC8C36E897 for ; Wed, 18 May 2016 16:47:28 +0000 (UTC) Received: by mail-wm0-x241.google.com with SMTP id g17so7759236wme.2 for ; Wed, 18 May 2016 09:47:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ffwll.ch; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=yYfEmc8iNh12cqKWV1tEOIbtpWGkAxmQhxd/hnyinsk=; b=khUOvFQZmXXUStffKEhpHCnvRsVCb97BUs9vTA2Emw336iAWrC31a9ql6MKcy9S8IH CSvhahTQGWP/kB5dfb9FCqJ7rqPTkQTuJJrJzmEVucSL4K745uhprKS4uDXth2bqewS3 cTB+BhQD0CsYmpmJanJgvMaPVHsoztIVEVilE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=yYfEmc8iNh12cqKWV1tEOIbtpWGkAxmQhxd/hnyinsk=; b=QBsliIjBXP2LM2PM7tfZrTShEoyEpDd1x7/jNDdPchthWB4o5Th3+AvzCPle1HlsOw LIeL5Iq5JwJh+kPu4TPO6Dew1XTR3G69e/Fmw6szwG3EVibQsKLtiRhmDALhJafJ1He0 N94HgqyrssKZbFvElLUIg0R/vU8NqdSUWiI/M+JkjxLLgHDgbfwbVN52fTNoseYheE7l c/IVSmB61QsWSEDyb7nKY+cfPs6llUAaSMohVamrD/uZgVUJ0PTTHf0a6Xu8OMYNb+5V R+gY2CbK1zGEHeBIioH2fIumaJkdJzWTOBNnEASmcG5hqtoO9LJ07+3iU3CSYH2rnPfV gUwg== X-Gm-Message-State: AOPr4FVazhPLoAF2e1DHIV+UiD3yTtDJhShwozfgCebbqf0lN+i0k2hnpPxIx+GXlXRvaQ== X-Received: by 10.28.175.83 with SMTP id y80mr8401779wme.8.1463590046605; Wed, 18 May 2016 09:47:26 -0700 (PDT) Received: from phenom.ffwll.local ([2a02:168:56b5:0:ac27:b86c:7764:9429]) by smtp.gmail.com with ESMTPSA id e8sm10093608wma.2.2016.05.18.09.47.25 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 18 May 2016 09:47:25 -0700 (PDT) From: Daniel Vetter To: Intel Graphics Development Date: Wed, 18 May 2016 18:47:12 +0200 Message-Id: <1463590036-17824-3-git-send-email-daniel.vetter@ffwll.ch> X-Mailer: git-send-email 2.8.1 In-Reply-To: <1463590036-17824-1-git-send-email-daniel.vetter@ffwll.ch> References: <1463590036-17824-1-git-send-email-daniel.vetter@ffwll.ch> Cc: Daniel Vetter , Rodrigo Vivi , "Pandiyan, Dhinakaran" , Daniel Vetter Subject: [Intel-gfx] [PATCH 3/7] drm/i915/psr: Make idle_frames sensible again X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-5.5 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This reverts commit dfaf37baa07513d2c37afff79978807d2d10221a Author: Rodrigo Vivi Date: Mon Dec 7 14:45:20 2015 -0800 drm/i915: Fix idle_frames counter. and commit 97173eaf5f33b1e85efdb06d593d333480b60bf3 Author: Rodrigo Vivi Date: Tue Jul 7 16:28:55 2015 -0700 drm/i915: PSR: Increase idle_frames and implements commit d44b4dcbd1b44737462b77971d216d21a9413341 Author: Rodrigo Vivi Date: Fri Nov 14 08:52:31 2014 -0800 drm/i915: HSW/BDW PSR Set idle_frames = VBT + 1 without the hack to use 2 idle frames when VBT says 1. We keep the + 1 just for safety, although I haven't really figured out why that one exists. It's nonsense. idle_frames = number of frames where the screen is entirely idle before we think about entering PSR. idle_patter = part of link training, and we probably totally butchered link training because we told the hw to entirely skip it. No wonder PSR occasionally just fell over. I suspect the reason we've increased idle frames is that it makes PSR entry slightly less likely, and more likely to happen in a quite system, which probably increased the changes the panel came back up without link training. The proper fix is to implement link training for PSR. Cc: Rodrigo Vivi Cc: Sonika Jindal Cc: Durgadoss R Cc: "Pandiyan, Dhinakaran" Signed-off-by: Daniel Vetter Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/i915/intel_psr.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c index a788d1e9589b..0295d8dd483f 100644 --- a/drivers/gpu/drm/i915/intel_psr.c +++ b/drivers/gpu/drm/i915/intel_psr.c @@ -272,14 +272,14 @@ static void hsw_psr_enable_source(struct intel_dp *intel_dp) struct drm_i915_private *dev_priv = dev->dev_private; uint32_t max_sleep_time = 0x1f; - /* - * Let's respect VBT in case VBT asks a higher idle_frame value. - * Let's use 6 as the minimum to cover all known cases including - * the off-by-one issue that HW has in some cases. Also there are - * cases where sink should be able to train - * with the 5 or 6 idle patterns. + /* Lately it was identified that depending on panel idle frame count + * calculated at HW can be off by 1. So let's use what came + * from VBT + 1. + * There are also other cases where panel demands at least 4 + * but VBT is not being set. To cover these 2 cases lets use + * at least 5 when VBT isn't set to be on the safest side. */ - uint32_t idle_frames = max(6, dev_priv->vbt.psr.idle_frames); + uint32_t idle_frames = dev_priv->vbt.psr.idle_frames + 1; uint32_t val = EDP_PSR_ENABLE; val |= max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT;