| Message ID | 1464359224-11436-14-git-send-email-mika.kuoppala@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
> + /* WaDisableDynamicCreditSharing:kbl */ > + if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0)) > + WA_SET_BIT(GAMT_CHKN_BIT_REG, (1 << 28)); > + Let's play name that bit! Otherwise the patch looks good, although slightly worrying that the hsd's state the WA is needed up to B0, but the WA db says up to A0... I guess we should rather trust the hsd's? Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Matthew Auld <matthew.william.auld@gmail.com> writes: > [ text/plain ] >> + /* WaDisableDynamicCreditSharing:kbl */ >> + if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0)) >> + WA_SET_BIT(GAMT_CHKN_BIT_REG, (1 << 28)); >> + > Let's play name that bit! > > Otherwise the patch looks good, although slightly worrying that the > hsd's state the WA is needed up to B0, but the WA db says up to A0... > > I guess we should rather trust the hsd's? Yes I consider hsd's the authoritative source. -Mika > > Reviewed-by: Matthew Auld <matthew.auld@intel.com>
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 14e0ec818ea4..e0441da08201 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1672,6 +1672,8 @@ enum skl_disp_power_wells { #define GEN7_TLB_RD_ADDR _MMIO(0x4700) +#define GAMT_CHKN_BIT_REG _MMIO(0x4ab8) + #if 0 #define PRB0_TAIL _MMIO(0x2030) #define PRB0_HEAD _MMIO(0x2034) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index dd743d988b1a..64a2dc47443d 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -1191,6 +1191,10 @@ static int kbl_init_workarounds(struct intel_engine_cs *engine) I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) | GEN9_GAPS_TSV_CREDIT_DISABLE)); + /* WaDisableDynamicCreditSharing:kbl */ + if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0)) + WA_SET_BIT(GAMT_CHKN_BIT_REG, (1 << 28)); + /* WaDisableFenceDestinationToSLM:kbl (pre-prod) */ if (IS_KBL_REVID(dev_priv, KBL_REVID_A0, KBL_REVID_A0)) WA_SET_BIT_MASKED(HDC_CHICKEN0,
Bspec states that we need to turn off dynamic credit sharing on kbl revid a0 and b0. This happens by writing bit 28 on 0x4ab8. References: HSD#2225601, HSD#2226938, HSD#2225763 Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com> --- drivers/gpu/drm/i915/i915_reg.h | 2 ++ drivers/gpu/drm/i915/intel_ringbuffer.c | 4 ++++ 2 files changed, 6 insertions(+)