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[25/25] drm/i915/kbl: Add WaClearSlmSpaceAtContextSwitch

Message ID 1464621067-25727-1-git-send-email-mika.kuoppala@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Mika Kuoppala May 30, 2016, 3:11 p.m. UTC 
This workaround for bdw and chv, is also needed for kbl A0.

References: HSD#1911519, BSID#569
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
---
 drivers/gpu/drm/i915/intel_lrc.c | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

Comments

Matthew Auld June 3, 2016, 4:01 p.m. UTC | #1 
What about skl, this also seems to need the WA until A0?
arun.siluvery@linux.intel.com June 4, 2016, 8:54 a.m. UTC | #2 
On 03/06/2016 21:31, Matthew Auld wrote:
> What about skl, this also seems to need the WA until A0?

SKL:A0 is pre-production stepping, it can be ignored.

regards
Arun

> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
Matthew Auld June 6, 2016, 10:04 a.m. UTC | #3 
On 4 June 2016 at 09:54, Arun Siluvery <arun.siluvery@linux.intel.com> wrote:
> On 03/06/2016 21:31, Matthew Auld wrote:
>>
>> What about skl, this also seems to need the WA until A0?
>
>
> SKL:A0 is pre-production stepping, it can be ignored.
>
> regards
> Arun
>
>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>>
>

In which case this patch is:

Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Mika Kuoppala June 6, 2016, 1 p.m. UTC | #4 
Arun Siluvery <arun.siluvery@linux.intel.com> writes:

> [ text/plain ]
> On 03/06/2016 21:31, Matthew Auld wrote:
>> What about skl, this also seems to need the WA until A0?
>
> SKL:A0 is pre-production stepping, it can be ignored.
>

Yes, the rationale here was that we have kbl:A0 around still
but there are no skl:A0 in use that we care.

-Mika


> regards
> Arun
>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>>
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 5b0f271b9d91..0612b6c8ffcf 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1261,6 +1261,22 @@  static int gen9_init_indirectctx_bb(struct intel_engine_cs *engine,
 		return ret;
 	index = ret;
 
+	/* WaClearSlmSpaceAtContextSwitch:kbl */
+	/* Actual scratch location is at 128 bytes offset */
+	if (IS_KBL_REVID(engine->i915, 0, KBL_REVID_A0)) {
+		uint32_t scratch_addr
+			= engine->scratch.gtt_offset + 2*CACHELINE_BYTES;
+
+		wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6));
+		wa_ctx_emit(batch, index, (PIPE_CONTROL_FLUSH_L3 |
+					   PIPE_CONTROL_GLOBAL_GTT_IVB |
+					   PIPE_CONTROL_CS_STALL |
+					   PIPE_CONTROL_QW_WRITE));
+		wa_ctx_emit(batch, index, scratch_addr);
+		wa_ctx_emit(batch, index, 0);
+		wa_ctx_emit(batch, index, 0);
+		wa_ctx_emit(batch, index, 0);
+	}
 	/* Pad to end of cacheline */
 	while (index % CACHELINE_DWORDS)
 		wa_ctx_emit(batch, index, MI_NOOP);