From patchwork Thu Jun 2 16:26:41 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Wang, Zhi A" X-Patchwork-Id: 9150875 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 1AA1C60467 for ; Thu, 2 Jun 2016 16:29:58 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0B6ED282ED for ; Thu, 2 Jun 2016 16:29:58 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 003F828310; Thu, 2 Jun 2016 16:29:57 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2C9DC282ED for ; Thu, 2 Jun 2016 16:29:57 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8F8E86E7D8; Thu, 2 Jun 2016 16:29:54 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTP id CBBC86E8A1 for ; Thu, 2 Jun 2016 16:29:46 +0000 (UTC) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga103.jf.intel.com with ESMTP; 02 Jun 2016 09:29:47 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.26,407,1459839600"; d="scan'208";a="979597856" Received: from zhiwang1-mobl4.ccr.corp.intel.com (HELO inno-VirtualBox.fi.intel.com) ([10.237.66.146]) by fmsmga001.fm.intel.com with ESMTP; 02 Jun 2016 09:29:45 -0700 From: Zhi Wang To: intel-gfx@lists.freedesktop.org, tvrtko.ursulin@linux.intel.com, joonas.lahtinen@linux.intel.com, kevin.tian@intel.com, zhiyuan.lv@intel.com, chris@chris-wilson.co.uk Date: Thu, 2 Jun 2016 12:26:41 -0400 Message-Id: <1464884806-3273-5-git-send-email-zhi.a.wang@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1464884806-3273-1-git-send-email-zhi.a.wang@intel.com> References: <1464884806-3273-1-git-send-email-zhi.a.wang@intel.com> Subject: [Intel-gfx] [PATCH 4/9] drm/i915: Introduce host graphics memory partition for GVT-g X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From: Bing Niu This patch introduces host graphics memory partition when GVT-g is enabled. Under GVT-g, i915 host driver only owned limited graphics resources, others are managed by GVT-g resource allocator and kept for other vGPUs. v6: - Remove kernel parameters used to configure GGTT owned by host. (Chris) - Other coding style comments from Chris. - Add more comments for reviewer. v3: - Remove fence partition, will use i915 fence stealing in future.(Kevin) - Santinize GVT host gm kernel parameters. (Joonas) v2: - Address all coding-style comments from Joonas previously. - Fix errors and warnning reported by checkpatch.pl. (Joonas) - Move the graphs into the header files. (Daniel) Signed-off-by: Bing Niu Signed-off-by: Zhi Wang --- drivers/gpu/drm/i915/i915_vgpu.c | 23 +++++++++++++++++------ drivers/gpu/drm/i915/intel_gvt.h | 25 +++++++++++++++++++++++++ 2 files changed, 42 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_vgpu.c b/drivers/gpu/drm/i915/i915_vgpu.c index 5312816..0d891a3 100644 --- a/drivers/gpu/drm/i915/i915_vgpu.c +++ b/drivers/gpu/drm/i915/i915_vgpu.c @@ -189,14 +189,25 @@ int intel_vgt_balloon(struct drm_i915_private *dev_priv) unsigned long unmappable_base, unmappable_size, unmappable_end; int ret; - if (!intel_vgpu_active(dev_priv)) + if (intel_gvt_active(dev_priv)) { + /* Retrieve GGTT partition information from macros */ + mappable_base = 0; + mappable_size = INTEL_GVT_HOST_LOW_GM_SIZE; + unmappable_base = dev_priv->ggtt.mappable_end; + unmappable_size = INTEL_GVT_HOST_HIGH_GM_SIZE; + } else if (intel_vgpu_active(dev_priv)) { + /* Retrieve GGTT partition information from PVINFO */ + mappable_base = I915_READ( + vgtif_reg(avail_rs.mappable_gmadr.base)); + mappable_size = I915_READ( + vgtif_reg(avail_rs.mappable_gmadr.size)); + unmappable_base = I915_READ( + vgtif_reg(avail_rs.nonmappable_gmadr.base)); + unmappable_size = I915_READ( + vgtif_reg(avail_rs.nonmappable_gmadr.size)); + } else return 0; - mappable_base = I915_READ(vgtif_reg(avail_rs.mappable_gmadr.base)); - mappable_size = I915_READ(vgtif_reg(avail_rs.mappable_gmadr.size)); - unmappable_base = I915_READ(vgtif_reg(avail_rs.nonmappable_gmadr.base)); - unmappable_size = I915_READ(vgtif_reg(avail_rs.nonmappable_gmadr.size)); - mappable_end = mappable_base + mappable_size; unmappable_end = unmappable_base + unmappable_size; diff --git a/drivers/gpu/drm/i915/intel_gvt.h b/drivers/gpu/drm/i915/intel_gvt.h index b9b361b..f0b9aac 100644 --- a/drivers/gpu/drm/i915/intel_gvt.h +++ b/drivers/gpu/drm/i915/intel_gvt.h @@ -24,6 +24,31 @@ #ifndef _INTEL_GVT_H_ #define _INTEL_GVT_H_ +/* + * Under GVT-g, i915 host driver only owned limited graphics resources, + * others are managed by GVT-g resource allocator and kept for other vGPUs. + * + * For graphics memory space partition, a typical layout looks like: + * + * +-------+-----------------------+------+-----------------------+ + * |* Host | *GVT-g Resource |* Host| *GVT-g Resource | + * | Owned | Allocator Managed | Owned| Allocator Managed | + * | | | | | + * +---------------+-------+----------------------+-------+-------+ + * | | | | | | | | | + * | i915 | vm 1 | vm 2 | vm 3 | i915 | vm 1 | vm 2 | vm 3 | + * | | | | | | | | | + * +-------+-------+-------+--------------+-------+-------+-------+ + * | Aperture | Hidden | + * +-------------------------------+------------------------------+ + * | GGTT memory space | + * +--------------------------------------------------------------+ + */ + +/* GGTT memory space owned by host */ +#define INTEL_GVT_HOST_LOW_GM_SIZE (96 * 1024 * 1024) +#define INTEL_GVT_HOST_HIGH_GM_SIZE (384 * 1024 * 1024) + #ifdef CONFIG_DRM_I915_GVT #include "gvt/gvt.h" extern int intel_gvt_init(struct drm_i915_private *dev_priv);