From patchwork Fri Jun 3 14:37:08 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Wilson X-Patchwork-Id: 9153293 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 10F0B60221 for ; Fri, 3 Jun 2016 14:38:23 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 01E342804C for ; Fri, 3 Jun 2016 14:38:23 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id EB2A3282E8; Fri, 3 Jun 2016 14:38:22 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6CA2626C9B for ; Fri, 3 Jun 2016 14:38:22 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0F0976EDED; Fri, 3 Jun 2016 14:38:02 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-wm0-x241.google.com (mail-wm0-x241.google.com [IPv6:2a00:1450:400c:c09::241]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4C3C16EDC2 for ; Fri, 3 Jun 2016 14:37:49 +0000 (UTC) Received: by mail-wm0-x241.google.com with SMTP id a136so24155447wme.0 for ; Fri, 03 Jun 2016 07:37:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=GNamhpe8KDEIqeWrDoSACqTjdl0oUHb27D1unhp6Lkc=; b=vswFgqn7EoTUi9C62MMd4DJCjL3AsUrn9IVb5v2A05YhNWuZucgBs3pgPGD5TI4za7 opMrESjDbC62z87AbKgavyJwjDTZRLKNFC0FLFBT9qA0k5E6hHLonblHpPizXhxZ8lPY O/Gupfcafe4eP3TSejHQEE9nf3xEzyPK6tpt3YnefCJzHZ/rdM8iAGHr/hokHn04eBvu H1t1gfDV/hBf2cU6lPxQqebSOta2tZ3ZrAPPwKInGXsYIB5PQhjGZfqXYSzI552Ir9VZ r86ocHwIV7CoL8EX+fN171mUSjzcZsJJuTgZ//XiLuV5wLFzfO9FGGHyvqG0U+7TypUr BZtg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=GNamhpe8KDEIqeWrDoSACqTjdl0oUHb27D1unhp6Lkc=; b=Do6aL/K+08uOyfJYy5FYlatX36XeGXEgjPRLdA9RMP2iD1Vt8dj9u2AjSqsP1M3UmO CowH47YwFu+UCIdOlNE5VzHTCs2n4hVbOAtY7cmrXxRZDBUTzU+sEGiMqVLFGzUK066D /dNzXIKSLnJpb50pN3BV9jFJvhdY4c++N2FZ9VXovn3+DbaqKBTJ0XVum3JYKmPXDtQm i8tYQKEnQb28mtw+Cd8VF19EqKaYDEFGGqJX8eo80DK9OYEhc9RqnQwaumRZqaoOAP9+ Fs1C7rbI9rfuqqk5y8+1C4+lnKSSUPf344y4ohlTui/52SXqa04vyvd97xKDgQSa42cr mpaw== X-Gm-Message-State: ALyK8tILvT19C67YrPjMCnsK8cZef02RB8zjxfJFC++LGp57sEgwyL3+pubJu5mkuVeldA== X-Received: by 10.194.116.195 with SMTP id jy3mr3765511wjb.137.1464964667321; Fri, 03 Jun 2016 07:37:47 -0700 (PDT) Received: from haswell.alporthouse.com ([78.156.65.138]) by smtp.gmail.com with ESMTPSA id e1sm6060275wjv.9.2016.06.03.07.37.46 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 03 Jun 2016 07:37:46 -0700 (PDT) From: Chris Wilson To: intel-gfx@lists.freedesktop.org Date: Fri, 3 Jun 2016 15:37:08 +0100 Message-Id: <1464964636-3877-26-git-send-email-chris@chris-wilson.co.uk> X-Mailer: git-send-email 2.8.1 In-Reply-To: <1464964636-3877-1-git-send-email-chris@chris-wilson.co.uk> References: <1464964636-3877-1-git-send-email-chris@chris-wilson.co.uk> Subject: [Intel-gfx] [PATCH v3 25/33] drm/i915: Move legacy kernel context pinning to intel_ringbuffer.c X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP This is so that we have symmetry with intel_lrc.c and avoid a source of if (i915.enable_execlists) layering violation within i915_gem_context.c - that is we move the specific handling of the dev_priv->kernel_context for legacy submission into the legacy submission code. This depends upon the init/fini ordering between contexts and engines already defined by intel_lrc.c, and also exporting the context alignment required for pinning the legacy context. v2: Separate out pin/unpin context funcs for greater symmetry with intel_lrc. One more step towards unifying behaviour between the two classes of engines and towards fixing another bug in i915_switch_context vs requests. Signed-off-by: Chris Wilson Reviewed-by: Joonas Lahtinen --- drivers/gpu/drm/i915/i915_drv.h | 2 ++ drivers/gpu/drm/i915/i915_gem_context.c | 27 ++-------------- drivers/gpu/drm/i915/intel_ringbuffer.c | 55 +++++++++++++++++++++++++++++++++ 3 files changed, 60 insertions(+), 24 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index f1c6c65c6a5e..bb1148b4966c 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -867,6 +867,8 @@ struct i915_gem_context { u32 user_handle; #define CONTEXT_NO_ZEROMAP (1<<0) + u32 ggtt_alignment; + struct intel_context { struct drm_i915_gem_object *state; struct intel_ringbuffer *ringbuf; diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c index a3b11aac23a4..c620fe6c9d96 100644 --- a/drivers/gpu/drm/i915/i915_gem_context.c +++ b/drivers/gpu/drm/i915/i915_gem_context.c @@ -268,6 +268,8 @@ __create_hw_context(struct drm_device *dev, list_add_tail(&ctx->link, &dev_priv->context_list); ctx->i915 = dev_priv; + ctx->ggtt_alignment = get_context_alignment(dev_priv); + if (dev_priv->hw_context_size) { struct drm_i915_gem_object *obj = i915_gem_alloc_context_obj(dev, dev_priv->hw_context_size); @@ -413,26 +415,6 @@ int i915_gem_context_init(struct drm_device *dev) return PTR_ERR(ctx); } - if (!i915.enable_execlists && ctx->engine[RCS].state) { - int ret; - - /* We may need to do things with the shrinker which - * require us to immediately switch back to the default - * context. This can cause a problem as pinning the - * default context also requires GTT space which may not - * be available. To avoid this we always pin the default - * context. - */ - ret = i915_gem_obj_ggtt_pin(ctx->engine[RCS].state, - get_context_alignment(dev_priv), 0); - if (ret) { - DRM_ERROR("Failed to pinned default global context (error %d)\n", - ret); - i915_gem_context_unreference(ctx); - return ret; - } - } - dev_priv->kernel_context = ctx; DRM_DEBUG_DRIVER("%s context support initialized\n", @@ -469,9 +451,6 @@ void i915_gem_context_fini(struct drm_device *dev) lockdep_assert_held(&dev->struct_mutex); - if (!i915.enable_execlists && dctx->engine[RCS].state) - i915_gem_object_ggtt_unpin(dctx->engine[RCS].state); - i915_gem_context_unreference(dctx); dev_priv->kernel_context = NULL; @@ -721,7 +700,7 @@ static int do_rcs_switch(struct drm_i915_gem_request *req) /* Trying to pin first makes error handling easier. */ ret = i915_gem_obj_ggtt_pin(to->engine[RCS].state, - get_context_alignment(engine->i915), + to->ggtt_alignment, 0); if (ret) return ret; diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 8d35a3978f9b..92bb376e5039 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -2240,6 +2240,47 @@ intel_ringbuffer_free(struct intel_ringbuffer *ring) kfree(ring); } +static int intel_ring_context_pin(struct i915_gem_context *ctx, + struct intel_engine_cs *engine) +{ + struct intel_context *ce = &ctx->engine[engine->id]; + int ret; + + lockdep_assert_held(&ctx->i915->dev->struct_mutex); + + if (ce->pin_count++) + return 0; + + if (ce->state) { + ret = i915_gem_obj_ggtt_pin(ce->state, ctx->ggtt_alignment, 0); + if (ret) + goto error; + } + + i915_gem_context_reference(ctx); + return 0; + +error: + ce->pin_count = 0; + return ret; +} + +static void intel_ring_context_unpin(struct i915_gem_context *ctx, + struct intel_engine_cs *engine) +{ + struct intel_context *ce = &ctx->engine[engine->id]; + + lockdep_assert_held(&ctx->i915->dev->struct_mutex); + + if (--ce->pin_count) + return; + + if (ce->state) + i915_gem_object_ggtt_unpin(ce->state); + + i915_gem_context_unreference(ctx); +} + static int intel_init_ring_buffer(struct drm_device *dev, struct intel_engine_cs *engine) { @@ -2260,6 +2301,17 @@ static int intel_init_ring_buffer(struct drm_device *dev, init_waitqueue_head(&engine->irq_queue); + /* We may need to do things with the shrinker which + * require us to immediately switch back to the default + * context. This can cause a problem as pinning the + * default context also requires GTT space which may not + * be available. To avoid this we always pin the default + * context. + */ + ret = intel_ring_context_pin(dev_priv->kernel_context, engine); + if (ret) + goto error; + ringbuf = intel_engine_create_ringbuffer(engine, 32 * PAGE_SIZE); if (IS_ERR(ringbuf)) { ret = PTR_ERR(ringbuf); @@ -2327,6 +2379,9 @@ void intel_cleanup_engine(struct intel_engine_cs *engine) i915_cmd_parser_fini_ring(engine); i915_gem_batch_pool_fini(&engine->batch_pool); + + intel_ring_context_unpin(dev_priv->kernel_context, engine); + engine->i915 = NULL; }