From patchwork Fri Jun 3 16:37:01 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Wilson X-Patchwork-Id: 9153595 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 8A3D26074E for ; Fri, 3 Jun 2016 16:38:52 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7AFDA26C9B for ; Fri, 3 Jun 2016 16:38:52 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 6FE7B28309; Fri, 3 Jun 2016 16:38:52 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id EB44826C9B for ; Fri, 3 Jun 2016 16:38:51 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 98A976EE49; Fri, 3 Jun 2016 16:38:42 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-wm0-x242.google.com (mail-wm0-x242.google.com [IPv6:2a00:1450:400c:c09::242]) by gabe.freedesktop.org (Postfix) with ESMTPS id 120EA6EE30 for ; Fri, 3 Jun 2016 16:38:10 +0000 (UTC) Received: by mail-wm0-x242.google.com with SMTP id a20so600968wma.3 for ; Fri, 03 Jun 2016 09:38:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=gq42/oLXVsGd5IyPxs/VIpZqkBHUbp4b7mq3I0WChdg=; b=syR4/KzMSvG5QsgMkzM6H5rzUPtSqyY+prMBxnqq7f7TXvx+1mn1ooeVPbftIhck7n KAdJVPgusJeFlp/OrM5aKvib+mzpVg3PgZ4YIywTE5o5r2uKrqrHU72jgeJHI4acxzx8 FgCh4XfGy9nowPi5+kJENb79m52ugUPKRHTdfJJnoY8bOkMx4TigV4WsE0sZyVXk7gOb 4550L1AeWNrN6KjSobWIYQtC9eSHGV8Xrq12+3yW2/X5qNVQbNo6zjDVn6/LeBkpok2K VvXi2F+uboIH35dr2FRX4D/oPgOazlArd7377lXMAeZWonG8gBe5tZARF1Eh4WWX98RK 1iKg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=gq42/oLXVsGd5IyPxs/VIpZqkBHUbp4b7mq3I0WChdg=; b=Tp7DHkwL4SZ9JV5iMEIKvUEvwDsyTKWiFcjhfoPFCgLtoumqMiULfvMAwhNL6bKjiJ 4Cm6PqgR+2ZkBrJxf/prONvoTJFQjbIxTqi2R4lDPt2+bEo/o1swwcGqcELHIPJUZpco F58nfhxleZbDgeoiX21HP3FrfO3gjvNz9OlJ86SOztDERB75C2DkkYARldag1foaCxAv w8qtnD9RYyX/385+j8Sbp0IEssg+b2aHy+dW6h1mZM5d9z+Slnk4vksOV3W/adwoejFh 70V+wdLTGi0Z7g+uIT2eNMY0Jbx47fen1mJs0p2/vU+58Ba0ZWXCbL0TE1msffvLovs0 K09g== X-Gm-Message-State: ALyK8tLsmmqYrfjgvPfOZp2PPwtnNdtmJxoqFDCOgRD1fanOWIHMR9dUdh9tRVdqoV5qpQ== X-Received: by 10.194.9.233 with SMTP id d9mr4973271wjb.29.1464971888255; Fri, 03 Jun 2016 09:38:08 -0700 (PDT) Received: from haswell.alporthouse.com ([78.156.65.138]) by smtp.gmail.com with ESMTPSA id l9sm6565607wjm.0.2016.06.03.09.38.07 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 03 Jun 2016 09:38:07 -0700 (PDT) From: Chris Wilson To: intel-gfx@lists.freedesktop.org Date: Fri, 3 Jun 2016 17:37:01 +0100 Message-Id: <1464971847-15809-37-git-send-email-chris@chris-wilson.co.uk> X-Mailer: git-send-email 2.8.1 In-Reply-To: <1464971847-15809-1-git-send-email-chris@chris-wilson.co.uk> References: <1464971847-15809-1-git-send-email-chris@chris-wilson.co.uk> Subject: [Intel-gfx] [PATCH 36/62] drm/i915: Convert engine->write_tail to operate on a request X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP If we rewrite the I915_WRITE_TAIL specialisation for the legacy ringbuffer as submitting the request onto the ringbuffer, we can unify the vfunc with both execlists and GuC in the next patch. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/i915_gem_request.c | 5 +-- drivers/gpu/drm/i915/intel_ringbuffer.c | 63 ++++++++++++++++++--------------- drivers/gpu/drm/i915/intel_ringbuffer.h | 3 +- 3 files changed, 36 insertions(+), 35 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem_request.c b/drivers/gpu/drm/i915/i915_gem_request.c index 06f724ee23dd..5fef1c291b25 100644 --- a/drivers/gpu/drm/i915/i915_gem_request.c +++ b/drivers/gpu/drm/i915/i915_gem_request.c @@ -461,11 +461,8 @@ void __i915_add_request(struct drm_i915_gem_request *request, if (i915.enable_execlists) ret = engine->emit_request(request); - else { + else ret = engine->add_request(request); - - request->tail = intel_ring_get_tail(ring); - } /* Not allowed to fail! */ WARN(ret, "emit|add_request failed: %d!\n", ret); /* Sanity check that the reserved size was large enough. */ diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 943dc08c69df..db38abddfec1 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -58,13 +58,6 @@ void intel_ring_update_space(struct intel_ring *ring) ring->tail, ring->size); } -static void __intel_engine_submit(struct intel_engine_cs *engine) -{ - struct intel_ring *ring = engine->buffer; - ring->tail &= ring->size - 1; - engine->write_tail(engine, ring->tail); -} - static int gen2_render_ring_flush(struct drm_i915_gem_request *req, u32 invalidate_domains, @@ -420,13 +413,6 @@ gen8_render_ring_flush(struct drm_i915_gem_request *req, return gen8_emit_pipe_control(req, flags, scratch_addr); } -static void ring_write_tail(struct intel_engine_cs *engine, - u32 value) -{ - struct drm_i915_private *dev_priv = engine->i915; - I915_WRITE_TAIL(engine, value); -} - u64 intel_engine_get_active_head(struct intel_engine_cs *engine) { struct drm_i915_private *dev_priv = engine->i915; @@ -535,7 +521,7 @@ static bool stop_ring(struct intel_engine_cs *engine) I915_WRITE_CTL(engine, 0); I915_WRITE_HEAD(engine, 0); - engine->write_tail(engine, 0); + I915_WRITE_TAIL(engine, 0); if (!IS_GEN2(dev_priv)) { (void)I915_READ_CTL(engine); @@ -1380,7 +1366,11 @@ gen6_add_request(struct drm_i915_gem_request *req) intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); intel_ring_emit(ring, req->fence.seqno); intel_ring_emit(ring, MI_USER_INTERRUPT); - __intel_engine_submit(req->engine); + intel_ring_advance(ring); + + req->tail = intel_ring_get_tail(ring); + + req->engine->submit_request(req); return 0; } @@ -1410,7 +1400,8 @@ gen8_render_add_request(struct drm_i915_gem_request *req) intel_ring_emit(ring, 0); intel_ring_emit(ring, MI_USER_INTERRUPT); intel_ring_emit(ring, MI_NOOP); - __intel_engine_submit(engine); + + req->engine->submit_request(req); return 0; } @@ -1632,11 +1623,21 @@ i9xx_add_request(struct drm_i915_gem_request *req) intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); intel_ring_emit(ring, req->fence.seqno); intel_ring_emit(ring, MI_USER_INTERRUPT); - __intel_engine_submit(req->engine); + intel_ring_advance(ring); + + req->tail = intel_ring_get_tail(ring); + + req->engine->submit_request(req); return 0; } +static void i9xx_submit_request(struct drm_i915_gem_request *request) +{ + struct drm_i915_private *dev_priv = request->i915; + I915_WRITE_TAIL(request->engine, request->tail); +} + static void gen6_ring_enable_irq(struct intel_engine_cs *engine) { @@ -2395,10 +2396,9 @@ void intel_engine_init_seqno(struct intel_engine_cs *engine, u32 seqno) engine->hangcheck.seqno = seqno; } -static void gen6_bsd_ring_write_tail(struct intel_engine_cs *engine, - u32 value) +static void gen6_bsd_submit_request(struct drm_i915_gem_request *request) { - struct drm_i915_private *dev_priv = engine->i915; + struct drm_i915_private *dev_priv = request->i915; /* Every tail move must follow the sequence below */ @@ -2418,8 +2418,8 @@ static void gen6_bsd_ring_write_tail(struct intel_engine_cs *engine, DRM_ERROR("timed out waiting for the BSD ring to wake up\n"); /* Now that the ring is fully powered up, update the tail */ - I915_WRITE_TAIL(engine, value); - POSTING_READ(RING_TAIL(engine->mmio_base)); + I915_WRITE_TAIL(request->engine, request->tail); + POSTING_READ(RING_TAIL(request->engine->mmio_base)); /* Let the ring send IDLE messages to the GT again, * and so let it sleep to conserve power when idle. @@ -2609,6 +2609,8 @@ int intel_init_render_ring_buffer(struct drm_device *dev) if (HAS_L3_DPF(dev_priv)) engine->irq_keep_mask = GT_RENDER_L3_PARITY_ERROR_INTERRUPT; + engine->submit_request = i9xx_submit_request; + if (INTEL_GEN(dev_priv) >= 8) { if (i915.semaphores) { obj = i915_gem_object_create(dev, 4096); @@ -2692,7 +2694,6 @@ int intel_init_render_ring_buffer(struct drm_device *dev) } engine->irq_enable_mask = I915_USER_INTERRUPT; } - engine->write_tail = ring_write_tail; if (IS_HASWELL(dev_priv)) engine->emit_bb_start = hsw_emit_bb_start; @@ -2736,12 +2737,13 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev) engine->exec_id = I915_EXEC_BSD; engine->hw_id = 1; - engine->write_tail = ring_write_tail; + engine->submit_request = i9xx_submit_request; + if (INTEL_GEN(dev_priv) >= 6) { engine->mmio_base = GEN6_BSD_RING_BASE; /* gen6 bsd needs a special wa for tail updates */ if (IS_GEN6(dev_priv)) - engine->write_tail = gen6_bsd_ring_write_tail; + engine->submit_request = gen6_bsd_submit_request; engine->emit_flush = gen6_bsd_ring_flush; engine->add_request = gen6_add_request; engine->irq_seqno_barrier = gen6_seqno_barrier; @@ -2810,10 +2812,11 @@ int intel_init_bsd2_ring_buffer(struct drm_device *dev) engine->exec_id = I915_EXEC_BSD; engine->hw_id = 4; - engine->write_tail = ring_write_tail; engine->mmio_base = GEN8_BSD2_RING_BASE; engine->emit_flush = gen6_bsd_ring_flush; engine->add_request = gen6_add_request; + engine->submit_request = i9xx_submit_request; + engine->irq_seqno_barrier = gen6_seqno_barrier; engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT; @@ -2841,9 +2844,10 @@ int intel_init_blt_ring_buffer(struct drm_device *dev) engine->hw_id = 2; engine->mmio_base = BLT_RING_BASE; - engine->write_tail = ring_write_tail; engine->emit_flush = gen6_ring_flush; engine->add_request = gen6_add_request; + engine->submit_request = i9xx_submit_request; + engine->irq_seqno_barrier = gen6_seqno_barrier; if (INTEL_GEN(dev_priv) >= 8) { engine->irq_enable_mask = @@ -2899,9 +2903,10 @@ int intel_init_vebox_ring_buffer(struct drm_device *dev) engine->hw_id = 3; engine->mmio_base = VEBOX_RING_BASE; - engine->write_tail = ring_write_tail; engine->emit_flush = gen6_ring_flush; engine->add_request = gen6_add_request; + engine->submit_request = i9xx_submit_request; + engine->irq_seqno_barrier = gen6_seqno_barrier; if (INTEL_GEN(dev_priv) >= 8) { diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h index 8b8e55a3e62e..647cc51e6457 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.h +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h @@ -212,8 +212,6 @@ struct intel_engine_cs { int (*init_context)(struct drm_i915_gem_request *req); - void (*write_tail)(struct intel_engine_cs *ring, - u32 value); int (*add_request)(struct drm_i915_gem_request *req); /* Some chipsets are not quite as coherent as advertised and need * an expensive kick to force a true read of the up-to-date seqno. @@ -302,6 +300,7 @@ struct intel_engine_cs { #define I915_DISPATCH_SECURE 0x1 #define I915_DISPATCH_PINNED 0x2 #define I915_DISPATCH_RS 0x4 + void (*submit_request)(struct drm_i915_gem_request *req); /** * List of objects currently involved in rendering from the