From patchwork Tue Jun 7 18:24:28 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 9162225 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 3AAB660777 for ; Tue, 7 Jun 2016 18:25:01 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3279728354 for ; Tue, 7 Jun 2016 18:25:01 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2705428358; Tue, 7 Jun 2016 18:25:01 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id DAB2728354 for ; Tue, 7 Jun 2016 18:25:00 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C67A26E811; Tue, 7 Jun 2016 18:24:55 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTP id D54D26E80F for ; Tue, 7 Jun 2016 18:24:47 +0000 (UTC) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga101.fm.intel.com with ESMTP; 07 Jun 2016 11:24:47 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.26,434,1459839600"; d="scan'208";a="992925041" Received: from ideak-desk.fi.intel.com ([10.237.72.61]) by orsmga002.jf.intel.com with ESMTP; 07 Jun 2016 11:24:35 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Date: Tue, 7 Jun 2016 21:24:28 +0300 Message-Id: <1465323873-9786-2-git-send-email-imre.deak@intel.com> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1465323873-9786-1-git-send-email-imre.deak@intel.com> References: <1465323873-9786-1-git-send-email-imre.deak@intel.com> Subject: [Intel-gfx] [PATCH 1/6] drm/i915/bxt: Wait for PHY1 GRC calibration synchronously X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP A follow-up patch moves the PHY enabling to the power well code where enabling/disabling the PHYs will happen independently. Because of this waiting for the GRC calibration in PHY1 asynchronously would need some additional logic. Instead of adding that let's keep things simple for now and wait synchronously. My measurements showed that the calibration takes ~4ms. Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/intel_ddi.c | 15 +++------------ 1 file changed, 3 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index 022b41d..b10c7b5 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -1899,8 +1899,6 @@ static void broxton_phy_init(struct drm_i915_private *dev_priv, * the corresponding calibrated value from PHY1, and disable * the automatic calibration on PHY0. */ - broxton_phy_wait_grc_done(dev_priv, DPIO_PHY1); - val = dev_priv->bxt_phy_grc = broxton_get_grc(dev_priv, DPIO_PHY1); grc_code = val << GRC_CODE_FAST_SHIFT | @@ -1912,14 +1910,13 @@ static void broxton_phy_init(struct drm_i915_private *dev_priv, val |= GRC_DIS | GRC_RDY_OVRD; I915_WRITE(BXT_PORT_REF_DW8(DPIO_PHY0), val); } - /* - * During PHY1 init delay waiting for GRC calibration to finish, since - * it can happen in parallel with the subsequent PHY0 init. - */ val = I915_READ(BXT_PHY_CTL_FAMILY(phy)); val |= COMMON_RESET_DIS; I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val); + + if (phy == DPIO_PHY1) + broxton_phy_wait_grc_done(dev_priv, DPIO_PHY1); } void broxton_ddi_phy_init(struct drm_i915_private *dev_priv) @@ -1927,12 +1924,6 @@ void broxton_ddi_phy_init(struct drm_i915_private *dev_priv) /* Enable PHY1 first since it provides Rcomp for PHY0 */ broxton_phy_init(dev_priv, DPIO_PHY1); broxton_phy_init(dev_priv, DPIO_PHY0); - - /* - * If BIOS enabled only PHY0 and not PHY1, we skipped waiting for the - * PHY1 GRC calibration to finish, so wait for it here. - */ - broxton_phy_wait_grc_done(dev_priv, DPIO_PHY1); } static void broxton_phy_uninit(struct drm_i915_private *dev_priv,