| Message ID | 1466088299-4792-1-git-send-email-mika.kuoppala@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
On 16/06/2016 15:44, Mika Kuoppala wrote: > Add WaDisableGatherAtSetShaderCommonSlice for all gen9 as stated > by bspec. > > References: HSD#2135817 > Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com> > --- > drivers/gpu/drm/i915/i915_reg.h | 1 + > drivers/gpu/drm/i915/intel_lrc.c | 7 +++++++ > 2 files changed, 8 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index d229a83ad70a..ff87d0b58d91 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -6117,6 +6117,7 @@ enum skl_disp_power_wells { > # define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1<<10) | (1<<26)) > # define GEN9_RHWO_OPTIMIZATION_DISABLE (1<<14) > #define COMMON_SLICE_CHICKEN2 _MMIO(0x7014) > +# define GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE (1<<12) > # define GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION (1<<8) > # define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE (1<<0) > > diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c > index 4fad8303648e..f4c7f7e6d523 100644 > --- a/drivers/gpu/drm/i915/intel_lrc.c > +++ b/drivers/gpu/drm/i915/intel_lrc.c > @@ -1285,6 +1285,13 @@ static int gen9_init_perctx_bb(struct intel_engine_cs *engine, > { > uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS); > > + /* WaDisableGatherAtSetShaderCommonSlice:skl,bxt,kbl */ > + wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1)); > + wa_ctx_emit_reg(batch, index, COMMON_SLICE_CHICKEN2); > + wa_ctx_emit(batch, index, _MASKED_BIT_DISABLE( > + GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE)); > + wa_ctx_emit(batch, index, MI_NOOP); > + The documentation says it is perctx wa batch but it is not correct, I got a clarification internally and they are trying to get it corrected. This needs to be applied in indirect context wa batch. regards Arun > /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */ > if (IS_SKL_REVID(engine->i915, 0, SKL_REVID_B0) || > IS_BXT_REVID(engine->i915, 0, BXT_REVID_A1)) { >
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index d229a83ad70a..ff87d0b58d91 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -6117,6 +6117,7 @@ enum skl_disp_power_wells { # define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1<<10) | (1<<26)) # define GEN9_RHWO_OPTIMIZATION_DISABLE (1<<14) #define COMMON_SLICE_CHICKEN2 _MMIO(0x7014) +# define GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE (1<<12) # define GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION (1<<8) # define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE (1<<0) diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 4fad8303648e..f4c7f7e6d523 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -1285,6 +1285,13 @@ static int gen9_init_perctx_bb(struct intel_engine_cs *engine, { uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS); + /* WaDisableGatherAtSetShaderCommonSlice:skl,bxt,kbl */ + wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1)); + wa_ctx_emit_reg(batch, index, COMMON_SLICE_CHICKEN2); + wa_ctx_emit(batch, index, _MASKED_BIT_DISABLE( + GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE)); + wa_ctx_emit(batch, index, MI_NOOP); + /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */ if (IS_SKL_REVID(engine->i915, 0, SKL_REVID_B0) || IS_BXT_REVID(engine->i915, 0, BXT_REVID_A1)) {
Add WaDisableGatherAtSetShaderCommonSlice for all gen9 as stated by bspec. References: HSD#2135817 Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com> --- drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_lrc.c | 7 +++++++ 2 files changed, 8 insertions(+)