[v2,02/15] drm/i915/tdr: Extend the idea of reset_counter to engine reset

Commit Message

[e-mail] June 17, 2016, 7:09 a.m. UTC

This change extends the idea of reset_counter variable to engine reset by
creating additional variables for each engine. Least significant bit is set
to mark the engine reset is pending and once reset is successful it is
incremented again, this is further used to count the no of engine resets.

Signed-off-by: Arun Siluvery <[e-mail]>
---
 drivers/gpu/drm/i915/i915_drv.h | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

Comments

Chris Wilson June 17, 2016, 7:35 a.m. UTC | #1

On Fri, Jun 17, 2016 at 08:09:02AM +0100, Arun Siluvery wrote:
> This change extends the idea of reset_counter variable to engine reset by
> creating additional variables for each engine. Least significant bit is set
> to mark the engine reset is pending and once reset is successful it is
> incremented again, this is further used to count the no of engine resets.

You still haven't split it up into the seperate fields.

atomic_t flags;
atomic_t global_reset_counter;
atomic_t engine_reset_counter[NUM_ENGINES];

That way checking whether a reset in progress is just one atomic read,
not N+1.
-Chris

Patch

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 9fa9698..8bb05b2 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1401,6 +1401,12 @@  struct i915_gpu_error {
 #define I915_RESET_IN_PROGRESS_FLAG	1
 #define I915_WEDGED			(1 << 31)
 
+	/* indicates request to reset engine */
+#define I915_ENGINE_RESET_IN_PROGRESS	(1<<0)
+
+	/* extending the idea of reset_counter to engine reset */
+	atomic_t engine_reset_counter[I915_NUM_ENGINES];
+
 	/**
 	 * Waitqueue to signal when the reset has completed. Used by clients
 	 * that wait for dev_priv->mm.wedged to settle.
@@ -3296,6 +3302,19 @@  static inline u32 i915_reset_count(struct i915_gpu_error *error)
 	return ((i915_reset_counter(error) & ~I915_WEDGED) + 1) / 2;
 }
 
+static inline bool i915_engine_reset_in_progress(struct i915_gpu_error *error,
+						 u32 engine_id)
+{
+	return unlikely(atomic_read(&error->engine_reset_counter[engine_id])
+			& I915_ENGINE_RESET_IN_PROGRESS);
+}
+
+static inline u32 i915_engine_reset_count(struct i915_gpu_error *error,
+					  struct intel_engine_cs *engine)
+{
+	return (atomic_read(&error->engine_reset_counter[engine->id]) + 1) / 2;
+}
+
 static inline bool i915_stop_ring_allow_ban(struct drm_i915_private *dev_priv)
 {
 	return dev_priv->gpu_error.stop_rings == 0 ||