From patchwork Mon Jun 20 13:08:27 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: tim.gore@intel.com X-Patchwork-Id: 9187387 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id F15946075F for ; Mon, 20 Jun 2016 13:08:33 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id DA52A27813 for ; Mon, 20 Jun 2016 13:08:33 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id CD3852793D; Mon, 20 Jun 2016 13:08:33 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 422CE27813 for ; Mon, 20 Jun 2016 13:08:33 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id EDE2189089; Mon, 20 Jun 2016 13:08:31 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTP id 9075C89ECD for ; Mon, 20 Jun 2016 13:08:29 +0000 (UTC) Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga101.fm.intel.com with ESMTP; 20 Jun 2016 06:08:29 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.26,498,1459839600"; d="scan'208";a="831684507" Received: from tgore-linux2.isw.intel.com ([10.102.226.150]) by orsmga003.jf.intel.com with ESMTP; 20 Jun 2016 06:08:29 -0700 From: tim.gore@intel.com To: intel-gfx@lists.freedesktop.org Date: Mon, 20 Jun 2016 14:08:27 +0100 Message-Id: <1466428107-2210-1-git-send-email-tim.gore@intel.com> X-Mailer: git-send-email 1.9.1 Subject: [Intel-gfx] [PATCH v2] drm/i915:gen9: implement WaMtpRenderPowerGatingBug X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From: Tim Gore This patch applies WaMtpRenderPowerGatingBug which overcomes a hang during mid thread pre-emption when running OCL test: test_allocations64.exe single 5 all. v2: Fix build break due to some git fail on my part Fix camel case variable names (Dave Gordon) Only apply to G0 stepping (Chris Harris) Signed-off-by: Tim Gore --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_reg.h | 5 ++++ drivers/gpu/drm/i915/intel_lrc.c | 57 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 63 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 25ebe46..c1f2d66 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -2717,6 +2717,7 @@ struct drm_i915_cmd_table { #define SKL_REVID_D0 0x3 #define SKL_REVID_E0 0x4 #define SKL_REVID_F0 0x5 +#define SKL_REVID_G0 0x6 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until)) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index c6bfbf8..a14e5a4 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -223,6 +223,11 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define GEN8_CONFIG0 _MMIO(0xD00) #define GEN9_DEFAULT_FIXES (1 << 3 | 1 << 2 | 1 << 1) +/* Slice GateWay mmio offset and related info*/ +#define GEN9_GW_DEST _MMIO(0xE220) +#define GEN9_GW_DATA_PAIRS 32 +#define GEN9_GW_PER_SLICE 3 + #define GAC_ECO_BITS _MMIO(0x14090) #define ECOBITS_SNB_BIT (1<<13) #define ECOBITS_PPGTT_CACHE64B (3<<8) diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index debed01..cc7dd1b 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -1261,6 +1261,53 @@ static int gen8_init_perctx_bb(struct intel_engine_cs *engine, return wa_ctx_end(wa_ctx, *offset = index, 1); } +/* Function to implement WaMtpRenderPowerGatingBug:skl */ +static int wa_mtp_render_power_gating(struct intel_engine_cs *engine, + uint32_t *const batch, uint32_t index) +{ + uint32_t num_lri = 0; + uint32_t gw_write_value = 0; + i915_reg_t gw_dest_mmio = {0}; + uint32_t i = 0; + uint32_t gw_count = 0; + uint32_t slice_count_max = engine->i915->info.slice_total; + uint32_t slice_count = 0; + + /* Slice count should be non-zero */ + WARN_ON(slice_count_max == 0); + + /* Mmios for GW are nice and sequential across slices, so we can + * just do this single slice logic 3 times and the 'DestMmio will + * be calculated properly' + */ + for (slice_count = 0; slice_count < slice_count_max; slice_count++) { + /* write the load reg immediate header */ + num_lri = (GEN9_GW_PER_SLICE * GEN9_GW_DATA_PAIRS) + 1; + wa_ctx_emit(batch, index, + MI_LOAD_REGISTER_IMM(num_lri) | MI_LRI_FORCE_POSTED); + + for (gw_count = 0; gw_count < GEN9_GW_PER_SLICE; gw_count++) { + gw_dest_mmio.reg = GEN9_GW_DEST.reg + (0x10 * gw_count) + + (0x40 * slice_count); + + for (i = 0; i < GEN9_GW_DATA_PAIRS; i++) { + // Read bits [31:24] from the Context Offset to [7:0] of LRI + // Read bit [13] from Context Offset to [31] of LRI + // Put i into bits [28:24] of LRI + gw_write_value = 0x1; + gw_write_value |= i << 24; + wa_ctx_emit_reg(batch, index, gw_dest_mmio); + wa_ctx_emit(batch, index, gw_write_value); + } + } + // Add one more 'dummy' data pair because the last MMIO in an LRI isn't actually 'posted' + wa_ctx_emit_reg(batch, index, gw_dest_mmio); + wa_ctx_emit(batch, index, gw_write_value); + } + return index; +} + + static int gen9_init_indirectctx_bb(struct intel_engine_cs *engine, struct i915_wa_ctx_bb *wa_ctx, uint32_t *const batch, @@ -1296,6 +1343,16 @@ static int gen9_init_indirectctx_bb(struct intel_engine_cs *engine, wa_ctx_emit(batch, index, 0); wa_ctx_emit(batch, index, 0); } + + /* WaMtpRenderPowerGatingBug:skl*/ + if (IS_SKL_REVID(engine->i915, 0, SKL_REVID_G0)) + { + ret = wa_mtp_render_power_gating(engine, batch, index); + if (ret < 0) + return ret; + } + index = ret; + /* Pad to end of cacheline */ while (index % CACHELINE_DWORDS) wa_ctx_emit(batch, index, MI_NOOP);