From patchwork Mon Jun 27 14:04:11 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tvrtko Ursulin X-Patchwork-Id: 9200675 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 2083A607D3 for ; Mon, 27 Jun 2016 14:05:36 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 123C928591 for ; Mon, 27 Jun 2016 14:05:36 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 06DB32859C; Mon, 27 Jun 2016 14:05:36 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.2 required=2.0 tests=BAYES_00,HK_RANDOM_FROM, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9F13128591 for ; Mon, 27 Jun 2016 14:05:32 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id AC8826E2E2; Mon, 27 Jun 2016 14:05:31 +0000 (UTC) X-Original-To: Intel-gfx@lists.freedesktop.org Delivered-To: Intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id 2A04E6E2DE for ; Mon, 27 Jun 2016 14:04:55 +0000 (UTC) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga102.jf.intel.com with ESMTP; 27 Jun 2016 07:04:28 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos; i="5.26,536,1459839600"; d="scan'208"; a="1005965192" Received: from tursulin-linux.isw.intel.com ([10.102.226.167]) by orsmga002.jf.intel.com with ESMTP; 27 Jun 2016 07:04:27 -0700 From: Tvrtko Ursulin To: Intel-gfx@lists.freedesktop.org Date: Mon, 27 Jun 2016 15:04:11 +0100 Message-Id: <1467036260-9252-5-git-send-email-tvrtko.ursulin@linux.intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1467036260-9252-1-git-send-email-tvrtko.ursulin@linux.intel.com> References: <1467036260-9252-1-git-send-email-tvrtko.ursulin@linux.intel.com> Subject: [Intel-gfx] [PATCH 04/13] drm/i915: Consolidate get and put irq vfuncs X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From: Tvrtko Ursulin Signed-off-by: Tvrtko Ursulin --- drivers/gpu/drm/i915/intel_ringbuffer.c | 46 ++++++++++++--------------------- 1 file changed, 17 insertions(+), 29 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index a4391cbbb2b6..5dddcdd2570d 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -2884,6 +2884,23 @@ static void intel_ring_default_vfuncs(struct drm_i915_private *dev_priv, } else { engine->add_request = i9xx_add_request; } + + if (INTEL_GEN(dev_priv) >= 8) { + engine->irq_get = gen8_ring_get_irq; + engine->irq_put = gen8_ring_put_irq; + } else if (INTEL_GEN(dev_priv) >= 6) { + engine->irq_get = gen6_ring_get_irq; + engine->irq_put = gen6_ring_put_irq; + } else if (IS_GEN5(dev_priv)) { + engine->irq_get = gen5_ring_get_irq; + engine->irq_put = gen5_ring_put_irq; + } else if (INTEL_GEN(dev_priv) >= 3) { + engine->irq_get = i9xx_ring_get_irq; + engine->irq_put = i9xx_ring_put_irq; + } else if (IS_GEN2(dev_priv)) { + engine->irq_get = i8xx_ring_get_irq; + engine->irq_put = i8xx_ring_put_irq; + } } int intel_init_render_ring_buffer(struct drm_device *dev) @@ -2922,8 +2939,6 @@ int intel_init_render_ring_buffer(struct drm_device *dev) engine->init_context = intel_rcs_ctx_init; engine->add_request = gen8_render_add_request; engine->flush = gen8_render_ring_flush; - engine->irq_get = gen8_ring_get_irq; - engine->irq_put = gen8_ring_put_irq; engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT; engine->get_seqno = ring_get_seqno; engine->set_seqno = ring_set_seqno; @@ -2938,8 +2953,6 @@ int intel_init_render_ring_buffer(struct drm_device *dev) engine->flush = gen7_render_ring_flush; if (IS_GEN6(dev_priv)) engine->flush = gen6_render_ring_flush; - engine->irq_get = gen6_ring_get_irq; - engine->irq_put = gen6_ring_put_irq; engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT; engine->get_seqno = ring_get_seqno; engine->set_seqno = ring_set_seqno; @@ -2969,8 +2982,6 @@ int intel_init_render_ring_buffer(struct drm_device *dev) engine->flush = gen4_render_ring_flush; engine->get_seqno = pc_render_get_seqno; engine->set_seqno = pc_render_set_seqno; - engine->irq_get = gen5_ring_get_irq; - engine->irq_put = gen5_ring_put_irq; engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT; } else { @@ -2980,13 +2991,6 @@ int intel_init_render_ring_buffer(struct drm_device *dev) engine->flush = gen4_render_ring_flush; engine->get_seqno = ring_get_seqno; engine->set_seqno = ring_set_seqno; - if (IS_GEN2(dev_priv)) { - engine->irq_get = i8xx_ring_get_irq; - engine->irq_put = i8xx_ring_put_irq; - } else { - engine->irq_get = i9xx_ring_get_irq; - engine->irq_put = i9xx_ring_put_irq; - } engine->irq_enable_mask = I915_USER_INTERRUPT; } @@ -3060,8 +3064,6 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev) if (INTEL_GEN(dev_priv) >= 8) { engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT; - engine->irq_get = gen8_ring_get_irq; - engine->irq_put = gen8_ring_put_irq; engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer; if (i915_semaphore_is_enabled(dev_priv)) { @@ -3071,8 +3073,6 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev) } } else { engine->irq_enable_mask = GT_BSD_USER_INTERRUPT; - engine->irq_get = gen6_ring_get_irq; - engine->irq_put = gen6_ring_put_irq; engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; if (i915_semaphore_is_enabled(dev_priv)) { @@ -3097,12 +3097,8 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev) engine->set_seqno = ring_set_seqno; if (IS_GEN5(dev_priv)) { engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT; - engine->irq_get = gen5_ring_get_irq; - engine->irq_put = gen5_ring_put_irq; } else { engine->irq_enable_mask = I915_BSD_USER_INTERRUPT; - engine->irq_get = i9xx_ring_get_irq; - engine->irq_put = i9xx_ring_put_irq; } engine->dispatch_execbuffer = i965_dispatch_execbuffer; } @@ -3132,8 +3128,6 @@ int intel_init_bsd2_ring_buffer(struct drm_device *dev) engine->set_seqno = ring_set_seqno; engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT; - engine->irq_get = gen8_ring_get_irq; - engine->irq_put = gen8_ring_put_irq; engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer; if (i915_semaphore_is_enabled(dev_priv)) { @@ -3165,8 +3159,6 @@ int intel_init_blt_ring_buffer(struct drm_device *dev) if (INTEL_GEN(dev_priv) >= 8) { engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT; - engine->irq_get = gen8_ring_get_irq; - engine->irq_put = gen8_ring_put_irq; engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer; if (i915_semaphore_is_enabled(dev_priv)) { engine->semaphore.sync_to = gen8_ring_sync; @@ -3175,8 +3167,6 @@ int intel_init_blt_ring_buffer(struct drm_device *dev) } } else { engine->irq_enable_mask = GT_BLT_USER_INTERRUPT; - engine->irq_get = gen6_ring_get_irq; - engine->irq_put = gen6_ring_put_irq; engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; if (i915_semaphore_is_enabled(dev_priv)) { engine->semaphore.signal = gen6_signal; @@ -3225,8 +3215,6 @@ int intel_init_vebox_ring_buffer(struct drm_device *dev) if (INTEL_GEN(dev_priv) >= 8) { engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT; - engine->irq_get = gen8_ring_get_irq; - engine->irq_put = gen8_ring_put_irq; engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer; if (i915_semaphore_is_enabled(dev_priv)) { engine->semaphore.sync_to = gen8_ring_sync;