From patchwork Fri Jul 1 16:23:23 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Wilson X-Patchwork-Id: 9210185 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id A5131607D8 for ; Fri, 1 Jul 2016 16:24:00 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 97C1C284EE for ; Fri, 1 Jul 2016 16:24:00 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 8C9B52868D; Fri, 1 Jul 2016 16:24:00 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2B75F284EE for ; Fri, 1 Jul 2016 16:24:00 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5F4526EAF9; Fri, 1 Jul 2016 16:23:59 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-wm0-x241.google.com (mail-wm0-x241.google.com [IPv6:2a00:1450:400c:c09::241]) by gabe.freedesktop.org (Postfix) with ESMTPS id 1BBC56EAF7 for ; Fri, 1 Jul 2016 16:23:55 +0000 (UTC) Received: by mail-wm0-x241.google.com with SMTP id c82so6412606wme.3 for ; Fri, 01 Jul 2016 09:23:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:subject:date:message-id:in-reply-to:references; bh=pNGDp3/Vg5T0HoatApEpLDq8/UPEC1ede7jjpG2VlB8=; b=wG9Yao9yoPmKq0EdLFb82uya7KoLCgG7WzZhZRPDcrkVEWJgOwDSGlbQK2RL9t9Mqx J3BeO0p5V4RHehVItOWp3Vejs5V+zHa486BzJ6/+gAeOHU/v7GU/Mo6qO3CrY4wgfvad 6fq73b95sZ7gKdN+cMthAhAFyFdyFZshSyankuFUBdHBcW8oAlXriV1t+LqAYkMOwfif RwhquYNVSM+gRDKWDvrclcj7zM5Ztmd3Vjo+RAjd/MQfjgfgGb4IvgJxJgPPnLVvGVtn bZi1GKx9v4TlEdlA4pwyy1XELZ/8EtEf7xgNS+LzqVn/QlbzNOk8FEs5iMgkOGRWVApO MMOw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:sender:from:to:subject:date:message-id :in-reply-to:references; bh=pNGDp3/Vg5T0HoatApEpLDq8/UPEC1ede7jjpG2VlB8=; b=hhKGfO7kkJCeVHvM7/GUHCthV5B+gHHaUuS7ZfMnQPxOIrdm3sZztC0wRCJJFbjufN F6PG3uSOhE2Go7m7L7x3QJfDek7b8odKncEy7oxlP5V2Me79m9499gOx4DQSStBLKEK6 bhgXKGkiIz4znO64Jqkv4MbZV9P96vWvXLW35WEVpXYGig2ipBojYX0YLZ9XLtGGRepR QaNRzaotNMJylLHsJ++N/XxosDM0gcqnd5dW48X27OB5RtN+DXiMwRPPs8SV58tffR6z LDX0tee2HVymTgiiYG3q7Mes1WXKlQFDXc8058A6Vjb+DLHECNwhjtZH8sSkXIvWW9Ts S2ew== X-Gm-Message-State: ALyK8tL4tSD1n196ModYC6NQtHhnjevmQkEiK8wLAdpMex+7Uiaf8AN4c0gFyyKmekSOmQ== X-Received: by 10.28.132.149 with SMTP id g143mr401491wmd.100.1467390233237; Fri, 01 Jul 2016 09:23:53 -0700 (PDT) Received: from haswell.alporthouse.com ([78.156.65.138]) by smtp.gmail.com with ESMTPSA id yr4sm6357408wjc.18.2016.07.01.09.23.52 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 01 Jul 2016 09:23:52 -0700 (PDT) From: Chris Wilson To: intel-gfx@lists.freedesktop.org Date: Fri, 1 Jul 2016 17:23:23 +0100 Message-Id: <1467390209-3576-14-git-send-email-chris@chris-wilson.co.uk> X-Mailer: git-send-email 2.8.1 In-Reply-To: <1467390209-3576-1-git-send-email-chris@chris-wilson.co.uk> References: <1467390209-3576-1-git-send-email-chris@chris-wilson.co.uk> Subject: [Intel-gfx] [CI 14/20] drm/i915: Only apply one barrier after a breadcrumb interrupt is posted X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP If we flag the seqno as potentially stale upon receiving an interrupt, we can use that information to reduce the frequency that we apply the heavyweight coherent seqno read (i.e. if we wake up a chain of waiters). v2: Use cmpxchg to replace READ_ONCE/WRITE_ONCE for more explicit control of the ordering wrt to interrupt generation and interrupt checking in the bottom-half. Signed-off-by: Chris Wilson Reviewed-by: Tvrtko Ursulin --- drivers/gpu/drm/i915/i915_drv.h | 15 ++++++++++++++- drivers/gpu/drm/i915/i915_irq.c | 1 + drivers/gpu/drm/i915/intel_breadcrumbs.c | 16 ++++++++++------ drivers/gpu/drm/i915/intel_ringbuffer.h | 1 + 4 files changed, 26 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index ee04bd40a41a..21181a6ec0b0 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -4005,7 +4005,20 @@ static inline bool __i915_request_irq_complete(struct drm_i915_gem_request *req) * but it is easier and safer to do it every time the waiter * is woken. */ - if (engine->irq_seqno_barrier) { + if (engine->irq_seqno_barrier && + cmpxchg_relaxed(&engine->irq_posted, 1, 0)) { + /* The ordering of irq_posted versus applying the barrier + * is crucial. The clearing of the current irq_posted must + * be visible before we perform the barrier operation, + * such that if a subsequent interrupt arrives, irq_posted + * is reasserted and our task rewoken (which causes us to + * do another __i915_request_irq_complete() immediately + * and reapply the barrier). Conversely, if the clear + * occurs after the barrier, then an interrupt that arrived + * whilst we waited on the barrier would not trigger a + * barrier on the next pass, and the read may not see the + * seqno update. + */ engine->irq_seqno_barrier(engine); if (i915_gem_request_completed(req)) return true; diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index be7f0b9b27e0..7724bae27bcf 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -976,6 +976,7 @@ static void ironlake_rps_change_irq_handler(struct drm_i915_private *dev_priv) static void notify_ring(struct intel_engine_cs *engine) { + smp_store_mb(engine->irq_posted, true); if (intel_engine_wakeup(engine)) { trace_i915_gem_request_notify(engine); engine->user_interrupts++; diff --git a/drivers/gpu/drm/i915/intel_breadcrumbs.c b/drivers/gpu/drm/i915/intel_breadcrumbs.c index f7fa99a00da8..31d3c06912dc 100644 --- a/drivers/gpu/drm/i915/intel_breadcrumbs.c +++ b/drivers/gpu/drm/i915/intel_breadcrumbs.c @@ -43,12 +43,18 @@ static void intel_breadcrumbs_fake_irq(unsigned long data) static void irq_enable(struct intel_engine_cs *engine) { + /* Enabling the IRQ may miss the generation of the interrupt, but + * we still need to force the barrier before reading the seqno, + * just in case. + */ + engine->irq_posted = true; WARN_ON(!engine->irq_get(engine)); } static void irq_disable(struct intel_engine_cs *engine) { engine->irq_put(engine); + engine->irq_posted = false; } static bool __intel_breadcrumbs_enable_irq(struct intel_breadcrumbs *b) @@ -56,7 +62,6 @@ static bool __intel_breadcrumbs_enable_irq(struct intel_breadcrumbs *b) struct intel_engine_cs *engine = container_of(b, struct intel_engine_cs, breadcrumbs); struct drm_i915_private *i915 = engine->i915; - bool irq_posted = false; assert_spin_locked(&b->lock); if (b->rpm_wakelock) @@ -72,10 +77,8 @@ static bool __intel_breadcrumbs_enable_irq(struct intel_breadcrumbs *b) /* No interrupts? Kick the waiter every jiffie! */ if (intel_irqs_enabled(i915)) { - if (!test_bit(engine->id, &i915->gpu_error.test_irq_rings)) { + if (!test_bit(engine->id, &i915->gpu_error.test_irq_rings)) irq_enable(engine); - irq_posted = true; - } b->irq_enabled = true; } @@ -83,7 +86,7 @@ static bool __intel_breadcrumbs_enable_irq(struct intel_breadcrumbs *b) test_bit(engine->id, &i915->gpu_error.missed_irq_rings)) mod_timer(&b->fake_irq, jiffies + 1); - return irq_posted; + return engine->irq_posted; } static void __intel_breadcrumbs_disable_irq(struct intel_breadcrumbs *b) @@ -205,7 +208,8 @@ static bool __intel_engine_add_wait(struct intel_engine_cs *engine, * in case the seqno passed. */ __intel_breadcrumbs_enable_irq(b); - wake_up_process(to_wait(next)->tsk); + if (READ_ONCE(engine->irq_posted)) + wake_up_process(to_wait(next)->tsk); } do { diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h index e7495a2d6367..f0447dc80e89 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.h +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h @@ -185,6 +185,7 @@ struct intel_engine_cs { struct i915_ctx_workarounds wa_ctx; unsigned irq_refcount; /* protected by dev_priv->irq_lock */ + bool irq_posted; u32 irq_enable_mask; /* bitmask to enable ring interrupt */ struct drm_i915_gem_request *trace_irq_req; bool __must_check (*irq_get)(struct intel_engine_cs *ring);