| Message ID | 1469036435-18918-24-git-send-email-carlos.santa@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
well... this is where one inheriting and extending the previous make it a bit ugly... you would need to set it to 0 at GEN5_FEATURES. maybe with a comment /* support discontinued */ On Wed, Jul 20, 2016 at 10:40 AM, Carlos Santa <carlos.santa@intel.com> wrote: > Moving all GPU features to the platform definition allows for > - standard place when adding new features from new platforms > - possible to see supported features when dumping struct > definitions > > Signed-off-by: Carlos Santa <carlos.santa@intel.com> > --- > drivers/gpu/drm/i915/i915_drv.h | 4 ++-- > drivers/gpu/drm/i915/i915_pci.c | 5 +++++ > 2 files changed, 7 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index 7075f76..b9d0478 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -784,6 +784,7 @@ struct intel_csr { > func(has_hw_contexts) sep \ > func(has_logical_ring_contexts) sep \ > func(has_l3_dpf) sep \ > + func(has_gmch_display) sep \ > func(has_resource_streamer) sep \ > func(has_pipe_cxsr) sep \ > func(has_hotplug) sep \ > @@ -2907,8 +2908,7 @@ struct drm_i915_cmd_table { > #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP) > #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE) > > -#define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || \ > - IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) > +#define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->has_gmch_display) > > /* DPF == dynamic parity feature */ > #define HAS_L3_DPF(dev) (INTEL_INFO(dev)->has_l3_dpf) > diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c > index c03cb97..59f3e35 100644 > --- a/drivers/gpu/drm/i915/i915_pci.c > +++ b/drivers/gpu/drm/i915/i915_pci.c > @@ -57,6 +57,7 @@ > #define GEN2_FEATURES \ > .gen = 2, .num_pipes = 1, \ > .has_overlay = 1, .overlay_needs_physical = 1, \ > + .has_gmch_display = 1, \ > .ring_mask = RENDER_RING, \ > GEN_DEFAULT_PIPEOFFSETS, \ > CURSOR_OFFSETS > @@ -84,6 +85,7 @@ static const struct intel_device_info intel_i865g_info = { > #define GEN3_FEATURES \ > .gen = 3, .num_pipes = 2, \ > .has_fw_blc = 1, \ > + .has_gmch_display = 1, \ > .ring_mask = RENDER_RING, \ > GEN_DEFAULT_PIPEOFFSETS, \ > CURSOR_OFFSETS > @@ -124,6 +126,7 @@ static const struct intel_device_info intel_i945gm_info = { > .gen = 4, .num_pipes = 2, \ > .has_hotplug = 1, \ > .has_fw_blc = 1, \ > + .has_gmch_display = 1, \ > GEN_DEFAULT_PIPEOFFSETS, \ > CURSOR_OFFSETS > > @@ -272,6 +275,7 @@ static const struct intel_device_info intel_ivybridge_q_info = { > .has_gmbus_irq = 1, \ > .has_fw_blc = 1, \ > .has_hw_contexts = 1, \ > + .has_gmch_display = 1, \ > .need_gfx_hws = 1, .has_hotplug = 1, \ > .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \ > .display_mmio_offset = VLV_DISPLAY_BASE, \ > @@ -357,6 +361,7 @@ static const struct intel_device_info intel_cherryview_info = { > .has_fw_blc = 1, > .has_hw_contexts = 1, > .has_logical_ring_contexts = 1, > + .has_gmch_display = 1, > .display_mmio_offset = VLV_DISPLAY_BASE, > GEN_CHV_PIPEOFFSETS, > CURSOR_OFFSETS, > -- > 1.9.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 7075f76..b9d0478 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -784,6 +784,7 @@ struct intel_csr { func(has_hw_contexts) sep \ func(has_logical_ring_contexts) sep \ func(has_l3_dpf) sep \ + func(has_gmch_display) sep \ func(has_resource_streamer) sep \ func(has_pipe_cxsr) sep \ func(has_hotplug) sep \ @@ -2907,8 +2908,7 @@ struct drm_i915_cmd_table { #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP) #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE) -#define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || \ - IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) +#define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->has_gmch_display) /* DPF == dynamic parity feature */ #define HAS_L3_DPF(dev) (INTEL_INFO(dev)->has_l3_dpf) diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index c03cb97..59f3e35 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -57,6 +57,7 @@ #define GEN2_FEATURES \ .gen = 2, .num_pipes = 1, \ .has_overlay = 1, .overlay_needs_physical = 1, \ + .has_gmch_display = 1, \ .ring_mask = RENDER_RING, \ GEN_DEFAULT_PIPEOFFSETS, \ CURSOR_OFFSETS @@ -84,6 +85,7 @@ static const struct intel_device_info intel_i865g_info = { #define GEN3_FEATURES \ .gen = 3, .num_pipes = 2, \ .has_fw_blc = 1, \ + .has_gmch_display = 1, \ .ring_mask = RENDER_RING, \ GEN_DEFAULT_PIPEOFFSETS, \ CURSOR_OFFSETS @@ -124,6 +126,7 @@ static const struct intel_device_info intel_i945gm_info = { .gen = 4, .num_pipes = 2, \ .has_hotplug = 1, \ .has_fw_blc = 1, \ + .has_gmch_display = 1, \ GEN_DEFAULT_PIPEOFFSETS, \ CURSOR_OFFSETS @@ -272,6 +275,7 @@ static const struct intel_device_info intel_ivybridge_q_info = { .has_gmbus_irq = 1, \ .has_fw_blc = 1, \ .has_hw_contexts = 1, \ + .has_gmch_display = 1, \ .need_gfx_hws = 1, .has_hotplug = 1, \ .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \ .display_mmio_offset = VLV_DISPLAY_BASE, \ @@ -357,6 +361,7 @@ static const struct intel_device_info intel_cherryview_info = { .has_fw_blc = 1, .has_hw_contexts = 1, .has_logical_ring_contexts = 1, + .has_gmch_display = 1, .display_mmio_offset = VLV_DISPLAY_BASE, GEN_CHV_PIPEOFFSETS, CURSOR_OFFSETS,
Moving all GPU features to the platform definition allows for - standard place when adding new features from new platforms - possible to see supported features when dumping struct definitions Signed-off-by: Carlos Santa <carlos.santa@intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 4 ++-- drivers/gpu/drm/i915/i915_pci.c | 5 +++++ 2 files changed, 7 insertions(+), 2 deletions(-)