diff mbox

[05/23] drm/i915: Move HAS_CSR definition to platform definition

Message ID 1469036435-18918-6-git-send-email-carlos.santa@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Santa, Carlos July 20, 2016, 5:40 p.m. UTC
Moving all GPU features to the platform struct definition allows for
	- standard place when adding new features from new platforms
	- possible to see supported features when dumping struct
	  definitions

Signed-off-by: Carlos Santa <carlos.santa@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h |  3 ++-
 drivers/gpu/drm/i915/i915_pci.c | 14 +++++++++-----
 2 files changed, 11 insertions(+), 6 deletions(-)

Comments

Rodrigo Vivi July 20, 2016, 9:04 p.m. UTC | #1
On Wed, Jul 20, 2016 at 10:40 AM, Carlos Santa <carlos.santa@intel.com> wrote:
> Moving all GPU features to the platform struct definition allows for
>         - standard place when adding new features from new platforms
>         - possible to see supported features when dumping struct
>           definitions
>
> Signed-off-by: Carlos Santa <carlos.santa@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h |  3 ++-
>  drivers/gpu/drm/i915/i915_pci.c | 14 +++++++++-----
>  2 files changed, 11 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 69e3818..db4930c 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -771,6 +771,7 @@ struct intel_csr {
>         func(has_psr) sep \
>         func(has_runtime_pm) sep \
>         func(has_core_ring_freq) sep \
> +       func(has_csr) sep \
>         func(has_pipe_cxsr) sep \
>         func(has_hotplug) sep \
>         func(cursor_needs_physical) sep \
> @@ -2854,7 +2855,7 @@ struct drm_i915_cmd_table {
>  #define HAS_RC6(dev)           (INTEL_INFO(dev)->gen >= 6)
>  #define HAS_RC6p(dev)          (IS_GEN6(dev) || IS_IVYBRIDGE(dev))
>
> -#define HAS_CSR(dev)   (IS_GEN9(dev))
> +#define HAS_CSR(dev)   (INTEL_INFO(dev)->has_csr)
>
>  /*
>   * For now, anything with a GuC requires uCode loading, and then supports
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 674b298..d266af5 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -324,22 +324,26 @@ static const struct intel_device_info intel_cherryview_info = {
>         CHV_COLORS,
>  };
>
> +#define GEN9_FEATURES  \
> +       .gen = 9, \
> +       .has_csr = 1
> +
>  static const struct intel_device_info intel_skylake_info = {
>         BDW_FEATURES,
> +       GEN9_FEATURES,

hmmm.. not sure about this GEN9_FEATURES along with BDW_FEATURES one...
Might be confusing and lead to mistakes.

I believe for now is better to spread the has_csr...

>         .is_skylake = 1,
> -       .gen = 9,
>  };
>
>  static const struct intel_device_info intel_skylake_gt3_info = {
>         BDW_FEATURES,
> +       GEN9_FEATURES,
>         .is_skylake = 1,
> -       .gen = 9,
>         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
>  };
>
>  static const struct intel_device_info intel_broxton_info = {
> +       GEN9_FEATURES,
>         .is_broxton = 1,
> -       .gen = 9,
>         .need_gfx_hws = 1, .has_hotplug = 1,
>         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
>         .num_pipes = 3,
> @@ -355,14 +359,14 @@ static const struct intel_device_info intel_broxton_info = {
>
>  static const struct intel_device_info intel_kabylake_info = {
>         BDW_FEATURES,
> +       GEN9_FEATURES,
>         .is_kabylake = 1,
> -       .gen = 9,
>  };
>
>  static const struct intel_device_info intel_kabylake_gt3_info = {
>         BDW_FEATURES,
> +       GEN9_FEATURES,
>         .is_kabylake = 1,
> -       .gen = 9,
>         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
>  };
>
> --
> 1.9.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 69e3818..db4930c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -771,6 +771,7 @@  struct intel_csr {
 	func(has_psr) sep \
 	func(has_runtime_pm) sep \
 	func(has_core_ring_freq) sep \
+	func(has_csr) sep \
 	func(has_pipe_cxsr) sep \
 	func(has_hotplug) sep \
 	func(cursor_needs_physical) sep \
@@ -2854,7 +2855,7 @@  struct drm_i915_cmd_table {
 #define HAS_RC6(dev)		(INTEL_INFO(dev)->gen >= 6)
 #define HAS_RC6p(dev)		(IS_GEN6(dev) || IS_IVYBRIDGE(dev))
 
-#define HAS_CSR(dev)	(IS_GEN9(dev))
+#define HAS_CSR(dev)	(INTEL_INFO(dev)->has_csr)
 
 /*
  * For now, anything with a GuC requires uCode loading, and then supports
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 674b298..d266af5 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -324,22 +324,26 @@  static const struct intel_device_info intel_cherryview_info = {
 	CHV_COLORS,
 };
 
+#define GEN9_FEATURES  \
+	.gen = 9, \
+	.has_csr = 1
+
 static const struct intel_device_info intel_skylake_info = {
 	BDW_FEATURES,
+	GEN9_FEATURES,
 	.is_skylake = 1,
-	.gen = 9,
 };
 
 static const struct intel_device_info intel_skylake_gt3_info = {
 	BDW_FEATURES,
+	GEN9_FEATURES,
 	.is_skylake = 1,
-	.gen = 9,
 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 };
 
 static const struct intel_device_info intel_broxton_info = {
+	GEN9_FEATURES,
 	.is_broxton = 1,
-	.gen = 9,
 	.need_gfx_hws = 1, .has_hotplug = 1,
 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 	.num_pipes = 3,
@@ -355,14 +359,14 @@  static const struct intel_device_info intel_broxton_info = {
 
 static const struct intel_device_info intel_kabylake_info = {
 	BDW_FEATURES,
+	GEN9_FEATURES,
 	.is_kabylake = 1,
-	.gen = 9,
 };
 
 static const struct intel_device_info intel_kabylake_gt3_info = {
 	BDW_FEATURES,
+	GEN9_FEATURES,
 	.is_kabylake = 1,
-	.gen = 9,
 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 };