From patchwork Fri Jul 22 14:10:45 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomeu Vizoso X-Patchwork-Id: 9243707 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 88FD1607D3 for ; Fri, 22 Jul 2016 14:11:43 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7AD5027FA5 for ; Fri, 22 Jul 2016 14:11:43 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 6FEBE27FA9; Fri, 22 Jul 2016 14:11:43 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED, T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E16E027FA5 for ; Fri, 22 Jul 2016 14:11:42 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3275E6EBAB; Fri, 22 Jul 2016 14:11:37 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-wm0-x243.google.com (mail-wm0-x243.google.com [IPv6:2a00:1450:400c:c09::243]) by gabe.freedesktop.org (Postfix) with ESMTPS id E7AE16EB9F; Fri, 22 Jul 2016 14:11:11 +0000 (UTC) Received: by mail-wm0-x243.google.com with SMTP id x83so6338244wma.3; Fri, 22 Jul 2016 07:11:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=9cQE7C3Y2KR4n8Piq0FNUOgdFjOpVRT3+KiYfbfpsxE=; b=Y3fVVIVyr2RvjhkbB4gVUaoYHJisacloFhIeML05U1l4uAbPl2Lc7m50HDedq5WDyg eLNJ+VzIvVwk48L9ag7aoWE2FEn03ezjUqRNB01qOzAJUmr9cWIqEs8HJrB1QfVeq6FW 38qfVyIHipKUBp4GpMAb5ZYlU5Uw/bRWWMycW/hV7S/eOP12wxxwzpVP0k8ok651SPUD k8PL05CRwuA+b7lZtF8IzYj6gOj1yVk6y26/1IhAU/R79WOQ2T7gC86iQEEjlqs9L0Ir 7sYyEcAE3IqUp7hAvHBPXYyODWXrVpo0HP01v9fQd8IzWKAB9OAW1lqTKFMV6scuPalZ 6x0g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=9cQE7C3Y2KR4n8Piq0FNUOgdFjOpVRT3+KiYfbfpsxE=; b=CenSUd2+I/euLFdEl2kBbvxNcsM1ycyAzwAEIBp9jemxQyANgO+JFiXK/lzbkdB6LP Dp5W4Kg0zrnSObHbp1HI1uV4jjAqoarATLV6KI9WnJI1z2IkRndDFGgSXJ4xP9Z24GJB klBjAxHhSzUTYzdk8LZeDJt2+cttgIJtVLo0N8Y1TmCIRDbpZRvGEMw31Jd0hACIJFQx nK/9Sawt4ORcrw6/enMsVsxqLCexIJK1qU8Rpzjtyx55TkFZ0q1q3C/AesicLHFGzfnJ uxNqt96J7Bd4OU/8dP1gy/asNKEdpYkfcJlguKJU+W3Vd9KU7tCf7ecpQ6RSBBEYD+WG hf4Q== X-Gm-Message-State: ALyK8tK3OVCro4z7i37ZIXvF7BdEt2pgyrME5fMu0XTPuvzXfISEv6CPOOA8ag8/38Tnyg== X-Received: by 10.28.48.202 with SMTP id w193mr14859012wmw.54.1469196669097; Fri, 22 Jul 2016 07:11:09 -0700 (PDT) Received: from cizrna.lan ([109.72.12.88]) by smtp.gmail.com with ESMTPSA id 3sm12799307wms.1.2016.07.22.07.11.07 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 22 Jul 2016 07:11:08 -0700 (PDT) From: Tomeu Vizoso To: linux-kernel@vger.kernel.org Date: Fri, 22 Jul 2016 16:10:45 +0200 Message-Id: <1469196645-3061-4-git-send-email-tomeu.vizoso@collabora.com> X-Mailer: git-send-email 2.5.5 In-Reply-To: <1469196645-3061-1-git-send-email-tomeu.vizoso@collabora.com> References: <1469196645-3061-1-git-send-email-tomeu.vizoso@collabora.com> Cc: Tomeu Vizoso , David Airlie , intel-gfx@lists.freedesktop.org, Thierry Reding , dri-devel@lists.freedesktop.org, Daniel Vetter , Emil Velikov Subject: [Intel-gfx] [PATCH v3 3/3] drm/i915: Use new CRC debugfs API X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP The core provides now an ABI to userspace for generation of frame CRCs, so implement the ->set_crc_source() callback and reuse as much code as possible with the previous ABI implementation. v2: - Leave the legacy implementation in place as the ABI implementation in the core is incompatible with it. v3: - Use the "cooked" vblank counter so we have a whole 32 bits. - Make sure we don't mess with the state of the legacy CRC capture ABI implementation. Signed-off-by: Tomeu Vizoso --- drivers/gpu/drm/i915/i915_irq.c | 69 ++++++++++++------- drivers/gpu/drm/i915/intel_display.c | 1 + drivers/gpu/drm/i915/intel_drv.h | 2 + drivers/gpu/drm/i915/intel_pipe_crc.c | 124 ++++++++++++++++++++++++---------- 4 files changed, 133 insertions(+), 63 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index b77d808b71cd..f2726171f7c8 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -1492,41 +1492,58 @@ static void display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, { struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; struct intel_pipe_crc_entry *entry; - int head, tail; + struct drm_crtc *crtc = intel_get_crtc_for_pipe(&dev_priv->drm, pipe); + struct drm_driver *driver = dev_priv->drm.driver; + uint32_t crcs[5]; + int head, tail, ret; spin_lock(&pipe_crc->lock); + if (pipe_crc->source) { + if (!pipe_crc->entries) { + spin_unlock(&pipe_crc->lock); + DRM_DEBUG_KMS("spurious interrupt\n"); + return; + } - if (!pipe_crc->entries) { - spin_unlock(&pipe_crc->lock); - DRM_DEBUG_KMS("spurious interrupt\n"); - return; - } - - head = pipe_crc->head; - tail = pipe_crc->tail; + head = pipe_crc->head; + tail = pipe_crc->tail; - if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) { - spin_unlock(&pipe_crc->lock); - DRM_ERROR("CRC buffer overflowing\n"); - return; - } + if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) { + spin_unlock(&pipe_crc->lock); + DRM_ERROR("CRC buffer overflowing\n"); + return; + } - entry = &pipe_crc->entries[head]; + entry = &pipe_crc->entries[head]; - entry->frame = dev_priv->drm.driver->get_vblank_counter(&dev_priv->drm, - pipe); - entry->crc[0] = crc0; - entry->crc[1] = crc1; - entry->crc[2] = crc2; - entry->crc[3] = crc3; - entry->crc[4] = crc4; + entry->frame = driver->get_vblank_counter(&dev_priv->drm, pipe); + entry->crc[0] = crc0; + entry->crc[1] = crc1; + entry->crc[2] = crc2; + entry->crc[3] = crc3; + entry->crc[4] = crc4; - head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1); - pipe_crc->head = head; + head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1); + pipe_crc->head = head; - spin_unlock(&pipe_crc->lock); + spin_unlock(&pipe_crc->lock); - wake_up_interruptible(&pipe_crc->wq); + wake_up_interruptible(&pipe_crc->wq); + } else { + spin_unlock(&pipe_crc->lock); + spin_lock(&crtc->crc.lock); + crcs[0] = crc0; + crcs[1] = crc1; + crcs[2] = crc2; + crcs[3] = crc3; + crcs[4] = crc4; + ret = drm_crtc_add_crc_entry(crtc, true, + drm_accurate_vblank_count(crtc), + crcs); + spin_unlock(&crtc->crc.lock); + if (!ret) + wake_up_interruptible(&crtc->crc.wq); + } } #else static inline void diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 111b350d1d7e..d91a2f779fb1 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -14019,6 +14019,7 @@ static const struct drm_crtc_funcs intel_crtc_funcs = { .page_flip = intel_crtc_page_flip, .atomic_duplicate_state = intel_crtc_duplicate_state, .atomic_destroy_state = intel_crtc_destroy_state, + .set_crc_source = intel_crtc_set_crc_source, }; /** diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 5d06cb2425a1..4302cf2cfb04 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -1782,6 +1782,8 @@ void intel_color_load_luts(struct drm_crtc_state *crtc_state); /* intel_pipe_crc.c */ int intel_pipe_crc_create(struct drm_minor *minor); void intel_pipe_crc_cleanup(struct drm_minor *minor); +int intel_crtc_set_crc_source(struct drm_crtc *crtc, const char *source_name, + size_t *values_cnt); extern const struct file_operations i915_display_crc_ctl_fops; #endif /* __INTEL_DRV_H__ */ diff --git a/drivers/gpu/drm/i915/intel_pipe_crc.c b/drivers/gpu/drm/i915/intel_pipe_crc.c index 4e6c28ce8ecf..d2f06a1a919a 100644 --- a/drivers/gpu/drm/i915/intel_pipe_crc.c +++ b/drivers/gpu/drm/i915/intel_pipe_crc.c @@ -624,15 +624,62 @@ static int ivb_pipe_crc_ctl_reg(struct drm_device *dev, return 0; } +static int do_set_crc_source(struct drm_device *dev, enum pipe pipe, + enum intel_pipe_crc_source source) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + struct intel_crtc *crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, + pipe)); + u32 val = 0; /* shut up gcc */ + int ret; + + if (IS_GEN2(dev)) + ret = i8xx_pipe_crc_ctl_reg(&source, &val); + else if (INTEL_INFO(dev)->gen < 5) + ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val); + else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) + ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val); + else if (IS_GEN5(dev) || IS_GEN6(dev)) + ret = ilk_pipe_crc_ctl_reg(&source, &val); + else + ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val); + + if (ret) + return ret; + + if (source) { + /* + * When IPS gets enabled, the pipe CRC changes. Since IPS gets + * enabled and disabled dynamically based on package C states, + * user space can't make reliable use of the CRCs, so let's just + * completely disable it. + */ + hsw_disable_ips(crtc); + } + + I915_WRITE(PIPE_CRC_CTL(pipe), val); + POSTING_READ(PIPE_CRC_CTL(pipe)); + + if (source == INTEL_PIPE_CRC_SOURCE_NONE) { + if (IS_G4X(dev)) + g4x_undo_pipe_scramble_reset(dev, pipe); + else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) + vlv_undo_pipe_scramble_reset(dev, pipe); + else if (IS_HASWELL(dev) && pipe == PIPE_A) + hsw_trans_edp_pipe_A_crc_wa(dev, false); + + hsw_enable_ips(crtc); + } + + return 0; +} + static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe, enum intel_pipe_crc_source source) { struct drm_i915_private *dev_priv = dev->dev_private; struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; - struct intel_crtc *crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, - pipe)); enum intel_display_power_domain power_domain; - u32 val = 0; /* shut up gcc */ int ret; if (pipe_crc->source == source) @@ -648,20 +695,6 @@ static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe, return -EIO; } - if (IS_GEN2(dev)) - ret = i8xx_pipe_crc_ctl_reg(&source, &val); - else if (INTEL_INFO(dev)->gen < 5) - ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val); - else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) - ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val); - else if (IS_GEN5(dev) || IS_GEN6(dev)) - ret = ilk_pipe_crc_ctl_reg(&source, &val); - else - ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val); - - if (ret != 0) - goto out; - /* none -> real source transition */ if (source) { struct intel_pipe_crc_entry *entries; @@ -677,14 +710,6 @@ static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe, goto out; } - /* - * When IPS gets enabled, the pipe CRC changes. Since IPS gets - * enabled and disabled dynamically based on package C states, - * user space can't make reliable use of the CRCs, so let's just - * completely disable it. - */ - hsw_disable_ips(crtc); - spin_lock_irq(&pipe_crc->lock); kfree(pipe_crc->entries); pipe_crc->entries = entries; @@ -693,10 +718,11 @@ static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe, spin_unlock_irq(&pipe_crc->lock); } - pipe_crc->source = source; + ret = do_set_crc_source(dev, pipe, source); + if (ret) + goto out; - I915_WRITE(PIPE_CRC_CTL(pipe), val); - POSTING_READ(PIPE_CRC_CTL(pipe)); + pipe_crc->source = source; /* real source -> none transition */ if (source == INTEL_PIPE_CRC_SOURCE_NONE) { @@ -720,15 +746,6 @@ static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe, spin_unlock_irq(&pipe_crc->lock); kfree(entries); - - if (IS_G4X(dev)) - g4x_undo_pipe_scramble_reset(dev, pipe); - else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) - vlv_undo_pipe_scramble_reset(dev, pipe); - else if (IS_HASWELL(dev) && pipe == PIPE_A) - hsw_trans_edp_pipe_A_crc_wa(dev, false); - - hsw_enable_ips(crtc); } ret = 0; @@ -821,6 +838,11 @@ display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s) { int i; + if (!buf) { + *s = INTEL_PIPE_CRC_SOURCE_NONE; + return 0; + } + for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++) if (!strcmp(buf, pipe_crc_sources[i])) { *s = i; @@ -949,3 +971,31 @@ void intel_pipe_crc_cleanup(struct drm_minor *minor) drm_debugfs_remove_files(info_list, 1, minor); } } + +int intel_crtc_set_crc_source(struct drm_crtc *crtc, const char *source_name, + size_t *values_cnt) +{ + struct drm_i915_private *dev_priv = crtc->dev->dev_private; + enum intel_display_power_domain power_domain; + enum intel_pipe_crc_source source; + int ret; + + if (display_crc_ctl_parse_source(source_name, &source) < 0) { + DRM_DEBUG_DRIVER("unknown source %s\n", source_name); + return -EINVAL; + } + + power_domain = POWER_DOMAIN_PIPE(crtc->index); + if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) { + DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n"); + return -EIO; + } + + ret = do_set_crc_source(crtc->dev, crtc->index, source); + + intel_display_power_put(dev_priv, power_domain); + + *values_cnt = 5; + + return ret; +}