From patchwork Mon Jul 25 16:29:45 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Gordon X-Patchwork-Id: 9246043 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 96FDA6077C for ; Mon, 25 Jul 2016 16:30:04 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7F59A1FF21 for ; Mon, 25 Jul 2016 16:30:04 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 73B722074F; Mon, 25 Jul 2016 16:30:04 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id F0FE21FF21 for ; Mon, 25 Jul 2016 16:30:03 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 969E46E38F; Mon, 25 Jul 2016 16:30:01 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTP id DC2026E38F for ; Mon, 25 Jul 2016 16:29:58 +0000 (UTC) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP; 25 Jul 2016 09:29:58 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos; i="5.28,420,1464678000"; d="scan'208"; a="1028766155" Received: from dsgordon-linux2.isw.intel.com ([10.102.226.88]) by fmsmga002.fm.intel.com with ESMTP; 25 Jul 2016 09:29:57 -0700 From: Dave Gordon To: intel-gfx@lists.freedesktop.org Date: Mon, 25 Jul 2016 17:29:45 +0100 Message-Id: <1469464185-15555-1-git-send-email-david.s.gordon@intel.com> X-Mailer: git-send-email 1.9.1 Organization: Intel Corporation (UK) Ltd. - Co. Reg. #1134945 - Pipers Way, Swindon SN3 1RJ Subject: [Intel-gfx] [PATCH] drm/i915: avoid "may be used uninitialised" warnings X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP gcc is getting false positives in its detection of uninitialised values. Specifically it thinks 'gtt_entry' can be used in a WARN_ON() macro without previously being assigned (the assigment is inside a conditional loop), bu actually the WARN_ON() can only be reached if the assignment has also been executed at least once. To avoid the annoying warning, though, this patch reorganises the code a little and adds an explicit initialisation of the suspect variable. Signed-off-by: Dave Gordon --- drivers/gpu/drm/i915/i915_gem_gtt.c | 19 ++++++++++++------- drivers/gpu/drm/i915/i915_gem_gtt.h | 1 + 2 files changed, 13 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index 30da543..90e1cf3 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -2368,7 +2368,7 @@ static void gen8_ggtt_insert_entries(struct i915_address_space *vm, struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm); struct sgt_iter sgt_iter; gen8_pte_t __iomem *gtt_entries; - gen8_pte_t gtt_entry; + gen8_pte_t gtt_entry = I915_NULL_PTE; dma_addr_t addr; int rpm_atomic_seq; int i = 0; @@ -2389,8 +2389,10 @@ static void gen8_ggtt_insert_entries(struct i915_address_space *vm, * of NUMA access patterns. Therefore, even with the way we assume * hardware should work, we must keep this posting read for paranoia. */ - if (i != 0) - WARN_ON(readq(>t_entries[i-1]) != gtt_entry); + if (i != 0) { + gen8_pte_t last_gtt_entry = readq(>t_entries[i-1]); + WARN_ON(last_gtt_entry != gtt_entry); + } /* This next bit makes the above posting read even more important. We * want to flush the TLBs only after we're certain all the PTE updates @@ -2465,7 +2467,7 @@ static void gen6_ggtt_insert_entries(struct i915_address_space *vm, struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm); struct sgt_iter sgt_iter; gen6_pte_t __iomem *gtt_entries; - gen6_pte_t gtt_entry; + gen6_pte_t gtt_entry = I915_NULL_PTE; dma_addr_t addr; int rpm_atomic_seq; int i = 0; @@ -2479,14 +2481,17 @@ static void gen6_ggtt_insert_entries(struct i915_address_space *vm, iowrite32(gtt_entry, >t_entries[i++]); } - /* XXX: This serves as a posting read to make sure that the PTE has + /* + * XXX: This serves as a posting read to make sure that the PTE has * actually been updated. There is some concern that even though * registers and PTEs are within the same BAR that they are potentially * of NUMA access patterns. Therefore, even with the way we assume * hardware should work, we must keep this posting read for paranoia. */ - if (i != 0) - WARN_ON(readl(>t_entries[i-1]) != gtt_entry); + if (i != 0) { + gen8_pte_t last_gtt_entry = readl(>t_entries[i-1]); + WARN_ON(last_gtt_entry != gtt_entry); + } /* This next bit makes the above posting read even more important. We * want to flush the TLBs only after we're certain all the PTE updates diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h index c4a6579..e088210 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.h +++ b/drivers/gpu/drm/i915/i915_gem_gtt.h @@ -54,6 +54,7 @@ typedef uint64_t gen8_ppgtt_pml4e_t; #define GEN6_PTE_UNCACHED (1 << 1) #define GEN6_PTE_VALID (1 << 0) +#define I915_NULL_PTE 0 #define I915_PTES(pte_len) (PAGE_SIZE / (pte_len)) #define I915_PTE_MASK(pte_len) (I915_PTES(pte_len) - 1) #define I915_PDES 512