| Message ID | 1470280061-640-2-git-send-email-dhinakaran.pandiyan@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Wed, Aug 03, 2016 at 08:07:38PM -0700, Dhinakaran Pandiyan wrote: > @@ -2588,7 +2592,7 @@ _intel_dp_set_link_train(struct intel_dp *intel_dp, > *DP |= DP_LINK_TRAIN_PAT_2_CPT; > break; > case DP_TRAINING_PATTERN_3: > - DRM_ERROR("DP training pattern 3 not supported\n"); > + DRM_ERROR("TPS3 not supported, using TPS2 instead\n"); > *DP |= DP_LINK_TRAIN_PAT_2_CPT; > break; > } > @@ -2613,7 +2617,7 @@ _intel_dp_set_link_train(struct intel_dp *intel_dp, > if (IS_CHERRYVIEW(dev)) { > *DP |= DP_LINK_TRAIN_PAT_3_CHV; > } else { > - DRM_ERROR("DP training pattern 3 not supported\n"); > + DRM_ERROR("TPS3 not supported, using TPS2 instead\n"); > *DP |= DP_LINK_TRAIN_PAT_2; Given that you have a fallback plan and if the fallback plan fails you alert the user with an error already, these aren't errors but debug. -Chris
On Thu, 2016-08-04 at 04:07 +0100, Chris Wilson wrote: > On Wed, Aug 03, 2016 at 08:07:38PM -0700, Dhinakaran Pandiyan wrote: > > @@ -2588,7 +2592,7 @@ _intel_dp_set_link_train(struct intel_dp *intel_dp, > > *DP |= DP_LINK_TRAIN_PAT_2_CPT; > > break; > > case DP_TRAINING_PATTERN_3: > > - DRM_ERROR("DP training pattern 3 not supported\n"); > > + DRM_ERROR("TPS3 not supported, using TPS2 instead\n"); > > *DP |= DP_LINK_TRAIN_PAT_2_CPT; > > break; > > } > > @@ -2613,7 +2617,7 @@ _intel_dp_set_link_train(struct intel_dp *intel_dp, > > if (IS_CHERRYVIEW(dev)) { > > *DP |= DP_LINK_TRAIN_PAT_3_CHV; > > } else { > > - DRM_ERROR("DP training pattern 3 not supported\n"); > > + DRM_ERROR("TPS3 not supported, using TPS2 instead\n"); > > *DP |= DP_LINK_TRAIN_PAT_2; > > Given that you have a fallback plan and if the fallback plan fails you > alert the user with an error already, these aren't errors but debug. > -Chris > I will make that change. Thanks for the review.
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 21b04c3..3ca33bd 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -2547,6 +2547,10 @@ _intel_dp_set_link_train(struct intel_dp *intel_dp, struct drm_i915_private *dev_priv = to_i915(dev); enum port port = intel_dig_port->port; + if (dp_train_pat & DP_TRAINING_PATTERN_MASK) + DRM_DEBUG_KMS("Using DP training pattern TPS%d\n", + dp_train_pat & DP_TRAINING_PATTERN_MASK); + if (HAS_DDI(dev)) { uint32_t temp = I915_READ(DP_TP_CTL(port)); @@ -2588,7 +2592,7 @@ _intel_dp_set_link_train(struct intel_dp *intel_dp, *DP |= DP_LINK_TRAIN_PAT_2_CPT; break; case DP_TRAINING_PATTERN_3: - DRM_ERROR("DP training pattern 3 not supported\n"); + DRM_ERROR("TPS3 not supported, using TPS2 instead\n"); *DP |= DP_LINK_TRAIN_PAT_2_CPT; break; } @@ -2613,7 +2617,7 @@ _intel_dp_set_link_train(struct intel_dp *intel_dp, if (IS_CHERRYVIEW(dev)) { *DP |= DP_LINK_TRAIN_PAT_3_CHV; } else { - DRM_ERROR("DP training pattern 3 not supported\n"); + DRM_ERROR("TPS3 not supported, using TPS2 instead\n"); *DP |= DP_LINK_TRAIN_PAT_2; } break; @@ -2629,11 +2633,8 @@ static void intel_dp_enable_port(struct intel_dp *intel_dp) to_intel_crtc(dp_to_dig_port(intel_dp)->base.base.crtc); /* enable with pattern 1 (as per spec) */ - _intel_dp_set_link_train(intel_dp, &intel_dp->DP, - DP_TRAINING_PATTERN_1); - I915_WRITE(intel_dp->output_reg, intel_dp->DP); - POSTING_READ(intel_dp->output_reg); + intel_dp_program_link_training_pattern(intel_dp, DP_TRAINING_PATTERN_1); /* * Magic for VLV/CHV. We _must_ first set up the register
Currently we do not print the training pattern used in any of the DP link training stages. Including this piece of information in debug messages will help debugging. Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> --- drivers/gpu/drm/i915/intel_dp.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-)