From patchwork Thu Aug 11 07:37:50 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: vathsala nagaraju X-Patchwork-Id: 9274577 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 4A5BF6022E for ; Thu, 11 Aug 2016 07:38:53 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3A404284E9 for ; Thu, 11 Aug 2016 07:38:53 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2F0922853A; Thu, 11 Aug 2016 07:38:53 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 9AA11284E9 for ; Thu, 11 Aug 2016 07:38:52 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id ECC326E8DF; Thu, 11 Aug 2016 07:38:51 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTP id 37E446E8DD for ; Thu, 11 Aug 2016 07:38:50 +0000 (UTC) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga103.fm.intel.com with ESMTP; 11 Aug 2016 00:38:50 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos; i="5.28,503,1464678000"; d="scan'208"; a="1033653917" Received: from vnagaraj-hp-elitedesk-800-g1-twr.iind.intel.com ([10.223.135.130]) by orsmga002.jf.intel.com with ESMTP; 11 Aug 2016 00:38:47 -0700 From: vathsala nagaraju To: intel-gfx@lists.freedesktop.org Date: Thu, 11 Aug 2016 13:07:50 +0530 Message-Id: <1470901072-17525-2-git-send-email-vathsala.nagaraju@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1470901072-17525-1-git-send-email-vathsala.nagaraju@intel.com> References: <1470901072-17525-1-git-send-email-vathsala.nagaraju@intel.com> Cc: rodrigo.vivi@intel.com Subject: [Intel-gfx] [PATCH 1/3] drm/i915/psr:Adds Y-cordinate to skl_psr_setup_vsc X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Adds Y-co-ordinate support to skl_psr_setup_vsc as per edp 1.4 spec,table 6-11:VSC SDP HEADER Extension for psr2 support. Cc: Rodrigo Vivi Signed-off-by: vathsala nagaraju --- drivers/gpu/drm/i915/i915_drv.h | 2 ++ drivers/gpu/drm/i915/intel_dp.c | 22 ++++++++++++++++++++++ drivers/gpu/drm/i915/intel_psr.c | 13 ++++++++++++- include/drm/drm_dp_helper.h | 5 ++++- 4 files changed, 40 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 7f2754a..79ce64f 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1022,6 +1022,8 @@ struct i915_psr { bool psr2_support; bool aux_frame_sync; bool link_standby; + bool y_cord_support; + bool colorimetry_support; }; enum intel_pch { diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 364db90..19e9ecf 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -3439,6 +3439,28 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp) dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync; DRM_DEBUG_KMS("PSR2 %s on sink", dev_priv->psr.psr2_support ? "supported" : "not supported"); + + if (dev_priv->psr.psr2_support) { + uint8_t psr_caps, dprx; + + /*check if panel supports Y-Cordinate*/ + drm_dp_dpcd_readb(&intel_dp->aux, + DP_PSR_CAPS, + &psr_caps); + if (psr_caps & DP_PSR_Y_COORDINATE) + dev_priv->psr.y_cord_support = true; + else + dev_priv->psr.y_cord_support = false; + /* check for COLORIMETRY SUPPORT */ + drm_dp_dpcd_readb(&intel_dp->aux, + DPRX_FEATURE_ENUMERATION_LIST, + &dprx); + if (dprx & VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED) + dev_priv->psr.colorimetry_support = true; + else + dev_priv->psr.colorimetry_support = false; + } + } /* Read the eDP Display control capabilities registers */ diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c index 59a21c9..76a630b 100644 --- a/drivers/gpu/drm/i915/intel_psr.c +++ b/drivers/gpu/drm/i915/intel_psr.c @@ -122,13 +122,24 @@ static void vlv_psr_setup_vsc(struct intel_dp *intel_dp) static void skl_psr_setup_su_vsc(struct intel_dp *intel_dp) { struct edp_vsc_psr psr_vsc; + struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); + struct drm_device *dev = intel_dig_port->base.base.dev; + struct drm_i915_private *dev_priv = to_i915(dev); /* Prepare VSC Header for SU as per EDP 1.4 spec, Table 6.11 */ memset(&psr_vsc, 0, sizeof(psr_vsc)); psr_vsc.sdp_header.HB0 = 0; psr_vsc.sdp_header.HB1 = 0x7; psr_vsc.sdp_header.HB2 = 0x3; - psr_vsc.sdp_header.HB3 = 0xb; + psr_vsc.sdp_header.HB3 = 0xc; + if (dev_priv->psr.y_cord_support && + dev_priv->psr.colorimetry_support) { + psr_vsc.sdp_header.HB2 = 0x5; + psr_vsc.sdp_header.HB3 = 0x13; + } else { + psr_vsc.sdp_header.HB2 = 0x4; + psr_vsc.sdp_header.HB3 = 0xe; + } intel_psr_write_vsc(intel_dp, &psr_vsc); } diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index 63b8bd5..3d875c0 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -194,7 +194,7 @@ # define DP_PSR_SETUP_TIME_0 (6 << 1) # define DP_PSR_SETUP_TIME_MASK (7 << 1) # define DP_PSR_SETUP_TIME_SHIFT 1 - +# define DP_PSR_Y_COORDINATE (1 << 4) /* * 0x80-0x8f describe downstream port capabilities, but there are two layouts * based on whether DP_DETAILED_CAP_INFO_AVAILABLE was set. If it was not, @@ -640,6 +640,9 @@ struct edp_sdp_header { #define EDP_SDP_HEADER_REVISION_MASK 0x1F #define EDP_SDP_HEADER_VALID_PAYLOAD_BYTES 0x1F +#define DPRX_FEATURE_ENUMERATION_LIST 0x02210 +#define VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED (1 << 3) + struct edp_vsc_psr { struct edp_sdp_header sdp_header; u8 DB0; /* Stereo Interface */