From patchwork Thu Aug 11 16:09:01 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: arun.siluvery@linux.intel.com X-Patchwork-Id: 9275515 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 29B3860231 for ; Thu, 11 Aug 2016 16:09:10 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1B78228710 for ; Thu, 11 Aug 2016 16:09:10 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 1012428713; Thu, 11 Aug 2016 16:09:10 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 9768728712 for ; Thu, 11 Aug 2016 16:09:09 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id CCE136E281; Thu, 11 Aug 2016 16:09:08 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTP id 338C56E281 for ; Thu, 11 Aug 2016 16:09:08 +0000 (UTC) Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga103.fm.intel.com with ESMTP; 11 Aug 2016 09:09:09 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.28,505,1464678000"; d="scan'208";a="747405824" Received: from asiluver-linux.isw.intel.com ([10.102.226.117]) by FMSMGA003.fm.intel.com with ESMTP; 11 Aug 2016 09:09:06 -0700 From: Arun Siluvery To: intel-gfx@lists.freedesktop.org Date: Thu, 11 Aug 2016 17:09:01 +0100 Message-Id: <1470931741-20353-3-git-send-email-arun.siluvery@linux.intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1470931741-20353-1-git-send-email-arun.siluvery@linux.intel.com> References: <1470931741-20353-1-git-send-email-arun.siluvery@linux.intel.com> Cc: Mika Kuoppala Subject: [Intel-gfx] [PATCH 2/2] drm/i915/error: capture errored context based on request context-id X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From: Dave Gordon Context capture hasn't worked for a while now, since the introduction of execlists because the function that records active context is using CCID register but this register contents are not valid in Execlist mode; this patch makes it work again by using a different way of identifying the context of interest in execlist mode. For: VIZ-2021 Cc: Chris Wilson Cc: Mika Kuoppala Signed-off-by: Dave Gordon Signed-off-by: Arun Siluvery --- drivers/gpu/drm/i915/i915_drv.h | 2 ++ drivers/gpu/drm/i915/i915_gpu_error.c | 46 +++++++++++++++++++++++++---------- 2 files changed, 35 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 7971c76..94b9314 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -546,6 +546,8 @@ struct drm_i915_error_state { u32 rc_psmi; /* sleep state */ u32 semaphore_mboxes[I915_NUM_ENGINES - 1]; + u64 ctx_desc; + struct drm_i915_error_object { int page_count; u64 gtt_offset; diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c index 3209f6a..fa365ee 100644 --- a/drivers/gpu/drm/i915/i915_gpu_error.c +++ b/drivers/gpu/drm/i915/i915_gpu_error.c @@ -386,7 +386,8 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf *m, err_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er); err_printf(m, "FORCEWAKE: 0x%08x\n", error->forcewake); err_printf(m, "DERRMR: 0x%08x\n", error->derrmr); - err_printf(m, "CCID: 0x%08x\n", error->ccid); + if (!i915.enable_execlists) + err_printf(m, "CCID: 0x%08x\n", error->ccid); err_printf(m, "Missed interrupts: 0x%08lx\n", dev_priv->gpu_error.missed_irq_rings); for (i = 0; i < dev_priv->num_fence_regs; i++) @@ -526,9 +527,10 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf *m, } if ((obj = ee->ctx)) { - err_printf(m, "%s --- HW Context = 0x%08x\n", + err_printf(m, "%s --- HW Context = 0x%08x, %d pages\n", dev_priv->engine[i].name, - lower_32_bits(obj->gtt_offset)); + lower_32_bits(obj->gtt_offset), + obj->page_count); print_error_obj(m, obj); } } @@ -1069,16 +1071,29 @@ static void i915_gem_record_active_context(struct intel_engine_cs *engine, { struct drm_i915_private *dev_priv = engine->i915; struct drm_i915_gem_object *obj; + bool elsp_mode = i915.enable_execlists; /* Currently render ring is the only HW context user */ - if (engine->id != RCS || !error->ccid) + if (engine->id != RCS) + return; + + /* contents of CCID are not valid in execlist mode of scheduling */ + if (!elsp_mode && !error->ccid) return; list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { + u64 base; + if (!i915_gem_obj_ggtt_bound(obj)) continue; - if ((error->ccid & PAGE_MASK) == i915_gem_obj_ggtt_offset(obj)) { + base = i915_gem_obj_ggtt_offset(obj); + + if (elsp_mode) + base += LRC_PPHWSP_PN * PAGE_SIZE; + + if (((error->ccid & PAGE_MASK) == base) || + (((base ^ ee->ctx_desc) & 0x00000000FFFFF000ULL) == 0)) { ee->ctx = i915_error_ggtt_object_create(dev_priv, obj); break; } @@ -1090,6 +1105,7 @@ static void i915_gem_record_rings(struct drm_i915_private *dev_priv, { struct i915_ggtt *ggtt = &dev_priv->ggtt; struct drm_i915_gem_request *request; + struct intel_engine_cs *engine; int i, count; if (dev_priv->semaphore_obj) { @@ -1098,17 +1114,12 @@ static void i915_gem_record_rings(struct drm_i915_private *dev_priv, dev_priv->semaphore_obj); } - for (i = 0; i < I915_NUM_ENGINES; i++) { - struct intel_engine_cs *engine = &dev_priv->engine[i]; + for_each_engine_masked(engine, dev_priv, dev_priv->gt.active_engines) { struct drm_i915_error_engine *ee = &error->engine[i]; + u64 ctx_desc; ee->pid = -1; - ee->engine_id = -1; - - if (!intel_engine_initialized(engine)) - continue; - - ee->engine_id = i; + ee->engine_id = engine->id; error_record_engine_registers(error, engine, ee); error_record_engine_waiters(engine, ee); @@ -1150,7 +1161,16 @@ static void i915_gem_record_rings(struct drm_i915_private *dev_priv, error->simulated |= request->ctx->flags & CONTEXT_NO_ERROR_CAPTURE; + ctx_desc = 0; + if (i915.enable_execlists) { + struct i915_gem_context *ctx; + + ctx = request ? request->ctx : dev_priv->kernel_context; + ctx_desc = intel_lr_context_descriptor(ctx, engine); + } + ring = request->ring; + ee->ctx_desc = ctx_desc; ee->cpu_ring_head = ring->head; ee->cpu_ring_tail = ring->tail; ee->ringbuffer =