| Message ID | 1471669765-5935-14-git-send-email-sagar.a.kamble@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Sat, Aug 20, 2016 at 10:39:12AM +0530, Sagar Arun Kamble wrote: > From: Tom O'Rourke <Tom.O'Rourke@intel.com> > > Send SLPC shutdown event during disable, suspend, and reset > operations. Sending shutdown event while already shutdown > is OK. > > v2: return void instead of ignored error code (Paulo) > > v5: Removed WARN_ON for checking msb of gtt address of > shared gem obj. (ChrisW) > Added SLPC state update during disable, suspend and reset. > Changed semantics of reset. It is supposed to just disable. (Sagar) > > Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com> > Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com> > --- > drivers/gpu/drm/i915/intel_slpc.c | 22 +++++++++++++++++++--- > 1 file changed, 19 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c > index 161cd13..5a1e6f2 100644 > --- a/drivers/gpu/drm/i915/intel_slpc.c > +++ b/drivers/gpu/drm/i915/intel_slpc.c > @@ -52,6 +52,19 @@ static void host2guc_slpc_reset(struct drm_i915_private *dev_priv) > host2guc_slpc(dev_priv, data, 4); > } > > +static void host2guc_slpc_shutdown(struct drm_i915_private *dev_priv) > +{ > + u32 data[4]; > + u32 shared_data_gtt_offset = i915_ggtt_offset(dev_priv->guc.slpc.vma); > + > + data[0] = HOST2GUC_ACTION_SLPC_REQUEST; > + data[1] = SLPC_EVENT(SLPC_EVENT_SHUTDOWN, 2); > + data[2] = shared_data_gtt_offset; > + data[3] = 0; > + > + host2guc_slpc(dev_priv, data, 4); > +} > + > static u8 slpc_get_platform_sku(struct drm_device *dev) > { > enum slpc_platform_sku platform_sku; > @@ -149,12 +162,14 @@ void intel_slpc_cleanup(struct drm_i915_private *dev_priv) > > void intel_slpc_suspend(struct drm_i915_private *dev_priv) > { > - return; > + host2guc_slpc_shutdown(dev_priv); > + dev_priv->guc.slpc.enabled = false; > } > > void intel_slpc_disable(struct drm_i915_private *dev_priv) > { > - return; > + host2guc_slpc_shutdown(dev_priv); > + dev_priv->guc.slpc.enabled = false; > } > > void intel_slpc_enable(struct drm_i915_private *dev_priv) > @@ -167,5 +182,6 @@ void intel_slpc_enable(struct drm_i915_private *dev_priv) > > void intel_slpc_reset(struct drm_i915_private *dev_priv) > { > - return; > + host2guc_slpc_shutdown(dev_priv); > + dev_priv->guc.slpc.enabled = false; > } Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c index 161cd13..5a1e6f2 100644 --- a/drivers/gpu/drm/i915/intel_slpc.c +++ b/drivers/gpu/drm/i915/intel_slpc.c @@ -52,6 +52,19 @@ static void host2guc_slpc_reset(struct drm_i915_private *dev_priv) host2guc_slpc(dev_priv, data, 4); } +static void host2guc_slpc_shutdown(struct drm_i915_private *dev_priv) +{ + u32 data[4]; + u32 shared_data_gtt_offset = i915_ggtt_offset(dev_priv->guc.slpc.vma); + + data[0] = HOST2GUC_ACTION_SLPC_REQUEST; + data[1] = SLPC_EVENT(SLPC_EVENT_SHUTDOWN, 2); + data[2] = shared_data_gtt_offset; + data[3] = 0; + + host2guc_slpc(dev_priv, data, 4); +} + static u8 slpc_get_platform_sku(struct drm_device *dev) { enum slpc_platform_sku platform_sku; @@ -149,12 +162,14 @@ void intel_slpc_cleanup(struct drm_i915_private *dev_priv) void intel_slpc_suspend(struct drm_i915_private *dev_priv) { - return; + host2guc_slpc_shutdown(dev_priv); + dev_priv->guc.slpc.enabled = false; } void intel_slpc_disable(struct drm_i915_private *dev_priv) { - return; + host2guc_slpc_shutdown(dev_priv); + dev_priv->guc.slpc.enabled = false; } void intel_slpc_enable(struct drm_i915_private *dev_priv) @@ -167,5 +182,6 @@ void intel_slpc_enable(struct drm_i915_private *dev_priv) void intel_slpc_reset(struct drm_i915_private *dev_priv) { - return; + host2guc_slpc_shutdown(dev_priv); + dev_priv->guc.slpc.enabled = false; }