From patchwork Sat Aug 20 05:09:00 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: sagar.a.kamble@intel.com X-Patchwork-Id: 9291539 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 1FAE660572 for ; Sat, 20 Aug 2016 05:07:21 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 11FB42947E for ; Sat, 20 Aug 2016 05:07:21 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 0705529488; Sat, 20 Aug 2016 05:07:21 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id A4AC72947E for ; Sat, 20 Aug 2016 05:07:20 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E92B96E35A; Sat, 20 Aug 2016 05:07:19 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTP id 49E1A6E357 for ; Sat, 20 Aug 2016 05:07:13 +0000 (UTC) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga103.jf.intel.com with ESMTP; 19 Aug 2016 22:07:10 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos; i="5.28,548,1464678000"; d="scan'208"; a="1038882849" Received: from sakamble-desktop.iind.intel.com ([10.223.82.59]) by orsmga002.jf.intel.com with ESMTP; 19 Aug 2016 22:07:08 -0700 From: Sagar Arun Kamble To: intel-gfx@lists.freedesktop.org Date: Sat, 20 Aug 2016 10:39:00 +0530 Message-Id: <1471669765-5935-2-git-send-email-sagar.a.kamble@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1471669765-5935-1-git-send-email-sagar.a.kamble@intel.com> References: <1471669765-5935-1-git-send-email-sagar.a.kamble@intel.com> Subject: [Intel-gfx] drm/i915: Remove RPM suspend dependency on rps.enabled and related changes X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP For Gen9, RPM suspend is failing if rps.enabled=false. This is needed for other platforms as RC6 and RPS enabling is indicated by rps.enabled. RPM Suspend depends only on RC6, so we need to remove the check of rps.enabled. For Gen9 RC6 and RPS enabling is separated hence do rps.enabled check only for non-Gen9 platforms. Once RC6 and RPS enabling is separated for other GENs this check can be completely removed. Moved setting of rps.enabled to platform level functions as there is case of disabling of RPS in gen9_enable_rps. Signed-off-by: Sagar Arun Kamble Reviewed-by: David Weinehall --- drivers/gpu/drm/i915/i915_drv.c | 10 +++++++++- drivers/gpu/drm/i915/intel_pm.c | 20 ++++++++++++++++++-- 2 files changed, 27 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 13ae340..bc2c67b 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -2284,9 +2284,17 @@ static int intel_runtime_suspend(struct device *device) struct drm_i915_private *dev_priv = to_i915(dev); int ret; - if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6()))) + if (WARN_ON_ONCE(!intel_enable_rc6())) return -ENODEV; + /* + * Once RC6 and RPS enabling is separated for non-GEN9 platforms + * below check should be removed. + */ + if (!IS_GEN9(dev)) + if (WARN_ON_ONCE(!dev_priv->rps.enabled)) + return -ENODEV; + if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev))) return -ENODEV; diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 99014d7..954e332 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4966,6 +4966,7 @@ static void gen9_disable_rc6(struct drm_i915_private *dev_priv) static void gen9_disable_rps(struct drm_i915_private *dev_priv) { I915_WRITE(GEN6_RP_CONTROL, 0); + dev_priv->rps.enabled = false; } static void gen6_disable_rps(struct drm_i915_private *dev_priv) @@ -4973,11 +4974,16 @@ static void gen6_disable_rps(struct drm_i915_private *dev_priv) I915_WRITE(GEN6_RC_CONTROL, 0); I915_WRITE(GEN6_RPNSWREQ, 1 << 31); I915_WRITE(GEN6_RP_CONTROL, 0); + + dev_priv->rps.enabled = false; + } static void cherryview_disable_rps(struct drm_i915_private *dev_priv) { I915_WRITE(GEN6_RC_CONTROL, 0); + + dev_priv->rps.enabled = false; } static void valleyview_disable_rps(struct drm_i915_private *dev_priv) @@ -4989,6 +4995,8 @@ static void valleyview_disable_rps(struct drm_i915_private *dev_priv) I915_WRITE(GEN6_RC_CONTROL, 0); intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); + + dev_priv->rps.enabled = false; } static void intel_print_rc6_info(struct drm_i915_private *dev_priv, u32 mode) @@ -5206,6 +5214,8 @@ static void gen9_enable_rps(struct drm_i915_private *dev_priv) reset_rps(dev_priv, gen6_set_rps); intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); + + dev_priv->rps.enabled = true; } static void gen9_enable_rc6(struct drm_i915_private *dev_priv) @@ -5349,6 +5359,8 @@ static void gen8_enable_rps(struct drm_i915_private *dev_priv) reset_rps(dev_priv, gen6_set_rps); intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); + + dev_priv->rps.enabled = true; } static void gen6_enable_rps(struct drm_i915_private *dev_priv) @@ -5445,6 +5457,8 @@ static void gen6_enable_rps(struct drm_i915_private *dev_priv) } intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); + + dev_priv->rps.enabled = true; } static void gen6_update_ring_freq(struct drm_i915_private *dev_priv) @@ -5919,6 +5933,8 @@ static void cherryview_enable_rps(struct drm_i915_private *dev_priv) reset_rps(dev_priv, valleyview_set_rps); intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); + + dev_priv->rps.enabled = true; } static void valleyview_enable_rps(struct drm_i915_private *dev_priv) @@ -5999,6 +6015,8 @@ static void valleyview_enable_rps(struct drm_i915_private *dev_priv) reset_rps(dev_priv, valleyview_set_rps); intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); + + dev_priv->rps.enabled = true; } static unsigned long intel_pxfreq(u32 vidfreq) @@ -6588,7 +6606,6 @@ void intel_disable_gt_powersave(struct drm_i915_private *dev_priv) ironlake_disable_drps(dev_priv); } - dev_priv->rps.enabled = false; mutex_unlock(&dev_priv->rps.hw_lock); } @@ -6632,7 +6649,6 @@ void intel_enable_gt_powersave(struct drm_i915_private *dev_priv) WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq); WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq); - dev_priv->rps.enabled = true; mutex_unlock(&dev_priv->rps.hw_lock); }