From patchwork Tue Aug 23 10:39:46 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: sagar.a.kamble@intel.com X-Patchwork-Id: 9295395 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 9FFDA60574 for ; Tue, 23 Aug 2016 10:38:12 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9037028B23 for ; Tue, 23 Aug 2016 10:38:12 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 8506028B92; Tue, 23 Aug 2016 10:38:12 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 3C56C28B23 for ; Tue, 23 Aug 2016 10:38:12 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A74196E5FB; Tue, 23 Aug 2016 10:38:10 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2606C6E5F9 for ; Tue, 23 Aug 2016 10:37:57 +0000 (UTC) Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga105.jf.intel.com with ESMTP; 23 Aug 2016 03:37:57 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.28,565,1464678000"; d="scan'208";a="869830245" Received: from sakamble-desktop.iind.intel.com ([10.223.82.59]) by orsmga003.jf.intel.com with ESMTP; 23 Aug 2016 03:37:57 -0700 From: Sagar Arun Kamble To: intel-gfx@lists.freedesktop.org Date: Tue, 23 Aug 2016 16:09:46 +0530 Message-Id: <1471948800-28641-14-git-send-email-sagar.a.kamble@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1471948800-28641-1-git-send-email-sagar.a.kamble@intel.com> References: <1471760418-27509-1-git-send-email-sagar.a.kamble@intel.com> <1471948800-28641-1-git-send-email-sagar.a.kamble@intel.com> Cc: Tom O'Rourke Subject: [Intel-gfx] [PATCH v3 13/27] drm/i915/slpc: Send reset event X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From: Tom O'Rourke Add host2guc SLPC reset event and send reset event during enable. v1: Extract host2guc_slpc to handle slpc status code coding style changes (Paulo) Removed WARN_ON for checking msb of gtt address of shared gem obj. (ChrisW) host2guc_action to i915_guc_action change.(Sagar) Updating SLPC enabled status. (Sagar) v2: Commit message update. (David) Reviewed-by: David Weinehall Signed-off-by: Tom O'Rourke Signed-off-by: Sagar Arun Kamble --- drivers/gpu/drm/i915/intel_slpc.c | 28 ++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_slpc.h | 14 ++++++++++++++ 2 files changed, 42 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c index ef29df1..b9e76f8 100644 --- a/drivers/gpu/drm/i915/intel_slpc.c +++ b/drivers/gpu/drm/i915/intel_slpc.c @@ -26,6 +26,32 @@ #include "i915_drv.h" #include "intel_guc.h" +static void host2guc_slpc(struct drm_i915_private *dev_priv, u32 *data, u32 len) +{ + int ret = i915_guc_action(&dev_priv->guc, data, len); + + if (!ret) { + ret = I915_READ(SOFT_SCRATCH(1)); + ret &= SLPC_EVENT_STATUS_MASK; + } + + if (ret) + DRM_ERROR("event 0x%x status %d\n", (data[1] >> 8), ret); +} + +static void host2guc_slpc_reset(struct drm_i915_private *dev_priv) +{ + u32 data[4]; + u32 shared_data_gtt_offset = i915_ggtt_offset(dev_priv->guc.slpc.vma); + + data[0] = HOST2GUC_ACTION_SLPC_REQUEST; + data[1] = SLPC_EVENT(SLPC_EVENT_RESET, 2); + data[2] = shared_data_gtt_offset; + data[3] = 0; + + host2guc_slpc(dev_priv, data, 4); +} + static unsigned int slpc_get_platform_sku(struct drm_i915_private *dev_priv) { enum slpc_platform_sku platform_sku; @@ -137,6 +163,8 @@ void intel_slpc_disable(struct drm_i915_private *dev_priv) void intel_slpc_enable(struct drm_i915_private *dev_priv) { + host2guc_slpc_reset(dev_priv); + dev_priv->guc.slpc.enabled = true; } void intel_slpc_reset(struct drm_i915_private *dev_priv) diff --git a/drivers/gpu/drm/i915/intel_slpc.h b/drivers/gpu/drm/i915/intel_slpc.h index e951289..031e36b 100644 --- a/drivers/gpu/drm/i915/intel_slpc.h +++ b/drivers/gpu/drm/i915/intel_slpc.h @@ -28,6 +28,20 @@ #define SLPC_MINOR_VER 4 #define SLPC_VERSION ((2015 << 16) | (SLPC_MAJOR_VER << 8) | (SLPC_MINOR_VER)) +enum slpc_event_id { + SLPC_EVENT_RESET = 0, + SLPC_EVENT_SHUTDOWN = 1, + SLPC_EVENT_PLATFORM_INFO_CHANGE = 2, + SLPC_EVENT_DISPLAY_MODE_CHANGE = 3, + SLPC_EVENT_FLIP_COMPLETE = 4, + SLPC_EVENT_QUERY_TASK_STATE = 5, + SLPC_EVENT_PARAMETER_SET = 6, + SLPC_EVENT_PARAMETER_UNSET = 7, +}; + +#define SLPC_EVENT(id, argc) ((u32) (id) << 8 | (argc)) +#define SLPC_EVENT_STATUS_MASK 0xFF + enum slpc_global_state { SLPC_GLOBAL_STATE_NOT_RUNNING = 0, SLPC_GLOBAL_STATE_INITIALIZING = 1,