@@ -4890,6 +4890,15 @@ i915_max_freq_set(void *data, u64 val)
dev_priv->rps.max_freq_softlimit = val;
+ if (intel_slpc_active(dev_priv)) {
+ intel_slpc_set_param(dev_priv,
+ SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ,
+ (u32) intel_gpu_freq(dev_priv, val));
+ intel_slpc_set_param(dev_priv,
+ SLPC_PARAM_GLOBAL_MAX_GT_SLICE_FREQ_MHZ,
+ (u32) intel_gpu_freq(dev_priv, val));
+ }
+
intel_set_rps(dev_priv, val);
mutex_unlock(&dev_priv->rps.hw_lock);
@@ -4945,6 +4954,15 @@ i915_min_freq_set(void *data, u64 val)
dev_priv->rps.min_freq_softlimit = val;
+ if (intel_slpc_active(dev_priv)) {
+ intel_slpc_set_param(dev_priv,
+ SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ,
+ (u32) intel_gpu_freq(dev_priv, val));
+ intel_slpc_set_param(dev_priv,
+ SLPC_PARAM_GLOBAL_MIN_GT_SLICE_FREQ_MHZ,
+ (u32) intel_gpu_freq(dev_priv, val));
+ }
+
intel_set_rps(dev_priv, val);
mutex_unlock(&dev_priv->rps.hw_lock);
@@ -417,6 +417,15 @@ static ssize_t gt_max_freq_mhz_store(struct device *kdev,
dev_priv->rps.max_freq_softlimit = val;
+ if (intel_slpc_active(dev_priv)) {
+ intel_slpc_set_param(dev_priv,
+ SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ,
+ (u32) intel_gpu_freq(dev_priv, val));
+ intel_slpc_set_param(dev_priv,
+ SLPC_PARAM_GLOBAL_MAX_GT_SLICE_FREQ_MHZ,
+ (u32) intel_gpu_freq(dev_priv, val));
+ }
+
val = clamp_t(int, dev_priv->rps.cur_freq,
dev_priv->rps.min_freq_softlimit,
dev_priv->rps.max_freq_softlimit);
@@ -470,6 +479,15 @@ static ssize_t gt_min_freq_mhz_store(struct device *kdev,
dev_priv->rps.min_freq_softlimit = val;
+ if (intel_slpc_active(dev_priv)) {
+ intel_slpc_set_param(dev_priv,
+ SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ,
+ (u32) intel_gpu_freq(dev_priv, val));
+ intel_slpc_set_param(dev_priv,
+ SLPC_PARAM_GLOBAL_MIN_GT_SLICE_FREQ_MHZ,
+ (u32) intel_gpu_freq(dev_priv, val));
+ }
+
val = clamp_t(int, dev_priv->rps.cur_freq,
dev_priv->rps.min_freq_softlimit,
dev_priv->rps.max_freq_softlimit);