| Message ID | 1471948800-28641-25-git-send-email-sagar.a.kamble@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index aaff409..77384b9 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -5158,7 +5158,13 @@ static void gen9_disable_rc6(struct drm_i915_private *dev_priv) static void gen9_disable_rps(struct drm_i915_private *dev_priv) { - I915_WRITE(GEN6_RP_CONTROL, 0); + uint32_t rp_ctl = 0; + + /* RP SW Mode Control will be needed for SLPC, Hence not clearing.*/ + if (i915.enable_slpc) + rp_ctl = I915_READ(GEN6_RP_CONTROL) & GEN6_RP_MEDIA_MODE_MASK; + + I915_WRITE(GEN6_RP_CONTROL, rp_ctl); dev_priv->rps.enabled = false; }
With SLPC, only RP SW Mode control should be left enabled by i915. Else, SLPC requests through through RPNSWREQ will not be granted. Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com> --- drivers/gpu/drm/i915/intel_pm.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-)