From patchwork Wed Sep 7 08:22:59 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: sagar.a.kamble@intel.com X-Patchwork-Id: 9318575 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 125676077F for ; Wed, 7 Sep 2016 08:21:13 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 045442857E for ; Wed, 7 Sep 2016 08:21:13 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id ED40A29120; Wed, 7 Sep 2016 08:21:12 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id A502E2857E for ; Wed, 7 Sep 2016 08:21:12 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3A2BA6E917; Wed, 7 Sep 2016 08:21:12 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id D13E36E915 for ; Wed, 7 Sep 2016 08:21:10 +0000 (UTC) Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga102.fm.intel.com with ESMTP; 07 Sep 2016 01:21:10 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.30,295,1470726000"; d="scan'208";a="5584983" Received: from sakamble-desktop.iind.intel.com ([10.223.82.59]) by orsmga005.jf.intel.com with ESMTP; 07 Sep 2016 01:21:09 -0700 From: Sagar Arun Kamble To: intel-gfx@lists.freedesktop.org Date: Wed, 7 Sep 2016 13:52:59 +0530 Message-Id: <1473236583-11533-22-git-send-email-sagar.a.kamble@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1473236583-11533-1-git-send-email-sagar.a.kamble@intel.com> References: <1471948800-28641-1-git-send-email-sagar.a.kamble@intel.com> <1473236583-11533-1-git-send-email-sagar.a.kamble@intel.com> Subject: [Intel-gfx] [PATCH v4 21/25] drm/i915/slpc: Update freq min/max softlimits X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP v2: Removing checks for vma obj and kmap_atomic validity. (Chris) v3: Rebase. v4: Updated to make sure SLPC enable keeps min/max freq softlimits unchanged after initializing once. (Chris) Signed-off-by: Sagar Arun Kamble --- drivers/gpu/drm/i915/intel_slpc.c | 47 +++++++++++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_slpc.h | 1 + 2 files changed, 48 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c index 60b3aaf..1a3a515 100644 --- a/drivers/gpu/drm/i915/intel_slpc.c +++ b/drivers/gpu/drm/i915/intel_slpc.c @@ -269,6 +269,7 @@ void intel_slpc_init(struct drm_i915_private *dev_priv) } slpc_shared_data_init(dev_priv); + dev_priv->guc.slpc.first_enable = false; } void intel_slpc_cleanup(struct drm_i915_private *dev_priv) @@ -279,6 +280,8 @@ void intel_slpc_cleanup(struct drm_i915_private *dev_priv) mutex_lock(&dev_priv->drm.struct_mutex); i915_vma_unpin_and_release(&guc->slpc.vma); mutex_unlock(&dev_priv->drm.struct_mutex); + + dev_priv->guc.slpc.first_enable = false; } void intel_slpc_suspend(struct drm_i915_private *dev_priv) @@ -339,4 +342,48 @@ void intel_slpc_enable(struct drm_i915_private *dev_priv) intel_slpc_set_param(dev_priv, SLPC_PARAM_GLOBAL_ENABLE_BALANCER_IN_NON_GAMING_MODE, 0); + + if (!dev_priv->guc.slpc.first_enable) { + struct drm_i915_gem_object *obj; + void *pv = NULL; + struct slpc_shared_data data; + + obj = dev_priv->guc.slpc.vma->obj; + intel_slpc_query_task_state(dev_priv); + + pv = kmap_atomic(i915_gem_object_get_page(obj, 0)); + data = *(struct slpc_shared_data *) pv; + kunmap_atomic(pv); + + /* + * TODO: Define separate variables for slice and unslice + * frequencies for driver state variable. + */ + dev_priv->rps.max_freq_softlimit = + data.task_state_data.freq_unslice_max; + dev_priv->rps.min_freq_softlimit = + data.task_state_data.freq_unslice_min; + + dev_priv->rps.max_freq_softlimit *= GEN9_FREQ_SCALER; + dev_priv->rps.min_freq_softlimit *= GEN9_FREQ_SCALER; + dev_priv->guc.slpc.first_enable = true; + } else { + /* Ask SLPC to operate within min/max freq softlimits */ + intel_slpc_set_param(dev_priv, + SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ, + (u32) intel_gpu_freq(dev_priv, + dev_priv->rps.max_freq_softlimit)); + intel_slpc_set_param(dev_priv, + SLPC_PARAM_GLOBAL_MAX_GT_SLICE_FREQ_MHZ, + (u32) intel_gpu_freq(dev_priv, + dev_priv->rps.max_freq_softlimit)); + intel_slpc_set_param(dev_priv, + SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ, + (u32) intel_gpu_freq(dev_priv, + dev_priv->rps.min_freq_softlimit)); + intel_slpc_set_param(dev_priv, + SLPC_PARAM_GLOBAL_MIN_GT_SLICE_FREQ_MHZ, + (u32) intel_gpu_freq(dev_priv, + dev_priv->rps.min_freq_softlimit)); + } } diff --git a/drivers/gpu/drm/i915/intel_slpc.h b/drivers/gpu/drm/i915/intel_slpc.h index 8436965..9a8602a 100644 --- a/drivers/gpu/drm/i915/intel_slpc.h +++ b/drivers/gpu/drm/i915/intel_slpc.h @@ -189,6 +189,7 @@ struct slpc_shared_data { struct intel_slpc { struct i915_vma *vma; bool enabled; + bool first_enable; }; /* intel_slpc.c */