| Message ID | 1473425505-3890-26-git-send-email-sagar.a.kamble@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Fri, Sep 09, 2016 at 06:21:44PM +0530, Sagar Arun Kamble wrote:
> With SLPC, user can read this value to know SLPC requested frequency.
Not SLPC specific, even elsewhere there may be a delay between the cur
value and the req (just means something more on SLPC).
Though I'm never keen on expanding the stable ABI, I can't object to
this given the existence of the others - but I will ask for a use case
other than debug.
-Chris
On 9/9/2016 10:13 PM, Chris Wilson wrote: > On Fri, Sep 09, 2016 at 06:21:44PM +0530, Sagar Arun Kamble wrote: >> With SLPC, user can read this value to know SLPC requested frequency. > Not SLPC specific, even elsewhere there may be a delay between the cur > value and the req (just means something more on SLPC). cur_freq is updated whenever RPNSWREQ is written so they should be same right? Where will delay come into picture? > > Though I'm never keen on expanding the stable ABI, I can't object to > this given the existence of the others - but I will ask for a use case > other than debug. For testing SLPC requests from Host side we have to rely on read of RPNSWREQ > -Chris >
On Thu, Sep 15, 2016 at 04:14:22PM +0530, Kamble, Sagar A wrote: > > > On 9/9/2016 10:13 PM, Chris Wilson wrote: > >On Fri, Sep 09, 2016 at 06:21:44PM +0530, Sagar Arun Kamble wrote: > >>With SLPC, user can read this value to know SLPC requested frequency. > >Not SLPC specific, even elsewhere there may be a delay between the cur > >value and the req (just means something more on SLPC). > cur_freq is updated whenever RPNSWREQ is written so they should be > same right? > Where will delay come into picture? RPNSWEQ is only updated from an irq worker. Plenty of scope for breakage. -Chris
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c index ab161ca..7bff742 100644 --- a/drivers/gpu/drm/i915/i915_sysfs.c +++ b/drivers/gpu/drm/i915/i915_sysfs.c @@ -307,6 +307,32 @@ static ssize_t gt_cur_freq_mhz_show(struct device *kdev, dev_priv->rps.cur_freq)); } +static ssize_t gt_req_freq_mhz_show(struct device *kdev, + struct device_attribute *attr, char *buf) +{ + struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); + u32 reqf; + + if (!intel_runtime_pm_get_if_in_use(dev_priv)) + return -ENODEV; + + reqf = I915_READ(GEN6_RPNSWREQ); + intel_runtime_pm_put(dev_priv); + + if (IS_GEN9(dev_priv)) + reqf >>= 23; + else { + reqf &= ~GEN6_TURBO_DISABLE; + if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) + reqf >>= 24; + else + reqf >>= 25; + } + reqf = intel_gpu_freq(dev_priv, reqf); + + return snprintf(buf, PAGE_SIZE, "%d\n", reqf); +} + static ssize_t gt_boost_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf) { struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev); @@ -481,6 +507,7 @@ static ssize_t gt_min_freq_mhz_store(struct device *kdev, static DEVICE_ATTR(gt_act_freq_mhz, S_IRUGO, gt_act_freq_mhz_show, NULL); static DEVICE_ATTR(gt_cur_freq_mhz, S_IRUGO, gt_cur_freq_mhz_show, NULL); +static DEVICE_ATTR(gt_req_freq_mhz, S_IRUGO, gt_req_freq_mhz_show, NULL); static DEVICE_ATTR(gt_boost_freq_mhz, S_IRUGO, gt_boost_freq_mhz_show, gt_boost_freq_mhz_store); static DEVICE_ATTR(gt_max_freq_mhz, S_IRUGO | S_IWUSR, gt_max_freq_mhz_show, gt_max_freq_mhz_store); static DEVICE_ATTR(gt_min_freq_mhz, S_IRUGO | S_IWUSR, gt_min_freq_mhz_show, gt_min_freq_mhz_store); @@ -513,6 +540,7 @@ static ssize_t gt_rp_mhz_show(struct device *kdev, struct device_attribute *attr static const struct attribute *gen6_attrs[] = { &dev_attr_gt_act_freq_mhz.attr, &dev_attr_gt_cur_freq_mhz.attr, + &dev_attr_gt_req_freq_mhz.attr, &dev_attr_gt_boost_freq_mhz.attr, &dev_attr_gt_max_freq_mhz.attr, &dev_attr_gt_min_freq_mhz.attr,
With SLPC, user can read this value to know SLPC requested frequency. Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com> --- drivers/gpu/drm/i915/i915_sysfs.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+)