From patchwork Mon Sep 19 17:15:02 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Praveen Paneri X-Patchwork-Id: 9339941 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 12251601C2 for ; Mon, 19 Sep 2016 17:11:46 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id F0DC328528 for ; Mon, 19 Sep 2016 17:11:45 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id E56B92876B; Mon, 19 Sep 2016 17:11:45 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 61EB528528 for ; Mon, 19 Sep 2016 17:11:45 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 014786E52F; Mon, 19 Sep 2016 17:11:44 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6BC126E52F for ; Mon, 19 Sep 2016 17:11:41 +0000 (UTC) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga105.jf.intel.com with ESMTP; 19 Sep 2016 10:11:40 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos; i="5.30,362,1470726000"; d="scan'208"; a="1059049395" Received: from intel-desktop.iind.intel.com ([10.223.82.55]) by fmsmga002.fm.intel.com with ESMTP; 19 Sep 2016 10:11:38 -0700 From: Praveen Paneri To: intel-gfx@lists.freedesktop.org Date: Mon, 19 Sep 2016 22:45:02 +0530 Message-Id: <1474305302-14503-1-git-send-email-praveen.paneri@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <57E01AE9.5030008@intel.com> References: <57E01AE9.5030008@intel.com> Cc: Zhe Wang , Praveen Paneri , Ankitprasad Sharma Subject: [Intel-gfx] [PATCH v2] drm/i915/bxt: Broxton decoupled MMIO X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Decoupled MMIO is an alternative way to access forcewake domain registers, which requires less cycles and avoids frequent software forcewake. v2: - Moved platform check out of the function and got rid of duplicate functions to find out decoupled power domain. - Added a check for forcewake already held and skipped decoupled access - Skipped writing 64 bit register through decoupled MMIO Signed-off-by: Zhe Wang Signed-off-by: Damien Lespiau Signed-off-by: Ankitprasad Sharma Signed-off-by: Praveen Paneri --- drivers/gpu/drm/i915/i915_drv.h | 11 ++++ drivers/gpu/drm/i915/i915_reg.h | 7 +++ drivers/gpu/drm/i915/intel_uncore.c | 118 +++++++++++++++++++++++++++++++++++- 3 files changed, 134 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 4dd307e..065247b 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -558,6 +558,16 @@ enum forcewake_domains { #define FW_REG_READ (1) #define FW_REG_WRITE (2) +enum power_domains { + GEN9_DECOUPLED_PD_BLITTER = 0, + GEN9_DECOUPLED_PD_RENDER, + GEN9_DECOUPLED_PD_MEDIA, + GEN9_DECOUPLED_PD_ALL +}; + +#define GEN9_DECOUPLED_OP_WRITE (0) +#define GEN9_DECOUPLED_OP_READ (1) + enum forcewake_domains intel_uncore_forcewake_for_reg(struct drm_i915_private *dev_priv, i915_reg_t reg, unsigned int op); @@ -2854,6 +2864,7 @@ struct drm_i915_cmd_table { #define GT_FREQUENCY_MULTIPLIER 50 #define GEN9_FREQ_SCALER 3 +#define HAS_DECOUPLED_MMIO(dev_priv) (IS_BROXTON(dev_priv) && IS_BXT_REVID(dev_priv, BXT_REVID_C0, REVID_FOREVER)) #include "i915_trace.h" static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 70d9616..be59803 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7394,6 +7394,13 @@ enum { #define SKL_FUSE_PG1_DIST_STATUS (1<<26) #define SKL_FUSE_PG2_DIST_STATUS (1<<25) +/* Decoupled MMIO register pair for kernel driver */ +#define GEN9_DECOUPLED_REG0_DW0 _MMIO(0xF00) +#define GEN9_DECOUPLED_REG0_DW1 _MMIO(0xF04) +#define GEN9_DECOUPLED_DW1_GO (1<<31) +#define GEN9_DECOUPLED_PD_SHIFT 28 +#define GEN9_DECOUPLED_OP_SHIFT 24 + /* Per-pipe DDI Function Control */ #define _TRANS_DDI_FUNC_CTL_A 0x60400 #define _TRANS_DDI_FUNC_CTL_B 0x61400 diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index a9b6c93..06fffba 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@ -816,6 +816,42 @@ unclaimed_reg_debug(struct drm_i915_private *dev_priv, __unclaimed_reg_debug(dev_priv, reg, read, before); } +/* + * Decoupled MMIO access for only 1 DWORD + */ +static void __gen9_decoupled_mmio_access(struct drm_i915_private *dev_priv, + uint32_t reg, u32 *ptr_data, + enum forcewake_domains fw_engine, int operation) +{ + enum power_domains pd_engine; + u32 ctrl_reg_data = 0; + + if (operation == GEN9_DECOUPLED_OP_WRITE) + __raw_i915_write32(dev_priv, + GEN9_DECOUPLED_REG0_DW0, + *ptr_data); + + pd_engine = (fw_engine == (FORCEWAKE_RENDER || FORCEWAKE_BLITTER)) ? \ + !(fw_engine >> 1) : (fw_engine >> 1); \ + + ctrl_reg_data |= reg; + ctrl_reg_data |= (operation << GEN9_DECOUPLED_OP_SHIFT); + ctrl_reg_data |= (pd_engine << GEN9_DECOUPLED_PD_SHIFT); + __raw_i915_write32(dev_priv, GEN9_DECOUPLED_REG0_DW1, ctrl_reg_data); + + ctrl_reg_data |= GEN9_DECOUPLED_DW1_GO; + __raw_i915_write32(dev_priv, GEN9_DECOUPLED_REG0_DW1, ctrl_reg_data); + + if (wait_for_atomic((__raw_i915_read32(dev_priv, + GEN9_DECOUPLED_REG0_DW1) & GEN9_DECOUPLED_DW1_GO) == 0, + FORCEWAKE_ACK_TIMEOUT_MS)) + DRM_ERROR("Decoupled MMIO wait timed out\n"); + + if (operation == GEN9_DECOUPLED_OP_READ) + *ptr_data = __raw_i915_read32(dev_priv, + GEN9_DECOUPLED_REG0_DW0); +} + #define GEN2_READ_HEADER(x) \ u##x val = 0; \ assert_rpm_wakelock_held(dev_priv); @@ -892,6 +928,20 @@ static inline void __force_wake_auto(struct drm_i915_private *dev_priv, dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_domains); } +static inline bool __is_forcewake_active(struct drm_i915_private *dev_priv, + enum forcewake_domains fw_domains) +{ + struct intel_uncore_forcewake_domain *domain; + + /* Ideally GCC would be constant-fold and eliminate this loop */ + for_each_fw_domain_masked(domain, fw_domains, dev_priv) { + if (domain->wake_count) + fw_domains &= ~domain->mask; + } + + return fw_domains ? 0 : 1; +} + #define __gen6_read(x) \ static u##x \ gen6_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \ @@ -940,6 +990,37 @@ gen9_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \ GEN6_READ_FOOTER; \ } +#define __gen9_decoupled_read(x) \ +static u##x \ +gen9_decoupled_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \ + enum forcewake_domains fw_engine; \ + GEN6_READ_HEADER(x); \ + fw_engine = __gen9_reg_read_fw_domains(offset); \ + if (fw_engine && x%32 == 0) { \ + if (__is_forcewake_active(dev_priv, fw_engine)) \ + __raw_i915_write##x(dev_priv, reg, val); \ + else { \ + unsigned i; \ + u32 *ptr_data = (u32 *) &val; \ + for (i = 0; i < x/32; i++) \ + __gen9_decoupled_mmio_access(dev_priv, \ + (offset + i*4), \ + ptr_data + i, \ + fw_engine, \ + GEN9_DECOUPLED_OP_READ); \ + } \ + } else { \ + if (fw_engine) \ + __force_wake_auto(dev_priv, fw_engine); \ + val = __raw_i915_read##x(dev_priv, reg); \ + } \ + GEN6_READ_FOOTER; \ +} + +__gen9_decoupled_read(8) +__gen9_decoupled_read(16) +__gen9_decoupled_read(32) +__gen9_decoupled_read(64) __gen9_read(8) __gen9_read(16) __gen9_read(32) @@ -1107,6 +1188,34 @@ gen9_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, \ GEN6_WRITE_FOOTER; \ } +#define __gen9_decoupled_write(x) \ +static void \ +gen9_decoupled_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, \ + bool trace) { \ + enum forcewake_domains fw_engine; \ + GEN6_WRITE_HEADER; \ + fw_engine = __gen9_reg_write_fw_domains(offset); \ + if (fw_engine && x == 32) { \ + u32 *ptr_data = (u32 *) &val; \ + if (__is_forcewake_active(dev_priv, fw_engine)) \ + __raw_i915_write##x(dev_priv, reg, val); \ + else \ + __gen9_decoupled_mmio_access(dev_priv, \ + offset, \ + ptr_data, \ + fw_engine, \ + GEN9_DECOUPLED_OP_WRITE); \ + } else { \ + if (fw_engine) \ + __force_wake_auto(dev_priv, fw_engine); \ + __raw_i915_write##x(dev_priv, reg, val); \ + } \ + GEN6_WRITE_FOOTER; \ +} + +__gen9_decoupled_write(8) +__gen9_decoupled_write(16) +__gen9_decoupled_write(32) __gen9_write(8) __gen9_write(16) __gen9_write(32) @@ -1328,8 +1437,13 @@ void intel_uncore_init(struct drm_i915_private *dev_priv) switch (INTEL_INFO(dev_priv)->gen) { default: case 9: - ASSIGN_WRITE_MMIO_VFUNCS(gen9); - ASSIGN_READ_MMIO_VFUNCS(gen9); + if (HAS_DECOUPLED_MMIO(dev_priv)) { + ASSIGN_WRITE_MMIO_VFUNCS(gen9_decoupled); + ASSIGN_READ_MMIO_VFUNCS(gen9_decoupled); + } else { + ASSIGN_WRITE_MMIO_VFUNCS(gen9); + ASSIGN_READ_MMIO_VFUNCS(gen9); + } break; case 8: if (IS_CHERRYVIEW(dev_priv)) {