From patchwork Tue Oct 4 04:47:58 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: meghanelogal X-Patchwork-Id: 9361125 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id CA6CA60752 for ; Tue, 4 Oct 2016 05:00:58 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id AC08D287EB for ; Tue, 4 Oct 2016 05:00:58 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 9D5A128ADE; Tue, 4 Oct 2016 05:00:58 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 906F928925 for ; Tue, 4 Oct 2016 05:00:57 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id CC06F6E118; Tue, 4 Oct 2016 05:00:54 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id 178866E118 for ; Tue, 4 Oct 2016 05:00:54 +0000 (UTC) Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga102.jf.intel.com with ESMTP; 03 Oct 2016 22:00:55 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.31,441,1473145200"; d="scan'208";a="886436087" Received: from meghanelogal-2012-client-platform.iind.intel.com ([10.223.25.121]) by orsmga003.jf.intel.com with ESMTP; 03 Oct 2016 22:00:50 -0700 From: meghanelogal To: intel-gfx@lists.freedesktop.org, daniel.vetter@ffwll.ch, chris@chris-wilson.co.uk, rodrigo.viv@intel.com Date: Tue, 4 Oct 2016 10:17:58 +0530 Message-Id: <1475556478-11331-1-git-send-email-megha.i.nelogal@intel.com> X-Mailer: git-send-email 1.9.1 Cc: paulo.r.zanoni@intel.com, meghanelogal Subject: [Intel-gfx] [PATCH] kms_atomic : Added subtest for Single Pipe DBUF validation X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Existing DDB algorithm divide the DDB wrt data rate, hence the planes with the less height but same width will be allocated less blocks and watermark are based on width which requires more DDB. With this data the flip may fail. In new DDB algorithm, the DDB is divided based on watermark requirement. In this subtest, dividing the htotal/200 will allocate ~2-4 blocks out of total(512/896), flip may fail with the exisiting algorithm.But with the new algorithm it will pass. Signed-off-by: Megha Nelogal --- tests/kms_atomic.c | 77 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 77 insertions(+) diff --git a/tests/kms_atomic.c b/tests/kms_atomic.c index f27ee46..ff25644 100644 --- a/tests/kms_atomic.c +++ b/tests/kms_atomic.c @@ -1280,6 +1280,60 @@ static void atomic_invalid_params(struct kms_atomic_crtc_state *crtc, do_ioctl_err(desc->fd, DRM_IOCTL_MODE_ATOMIC, &ioc, EFAULT); } +static void validate_dbuf(struct kms_atomic_crtc_state *crtc, + struct kms_atomic_plane_state **plane_array, + int plane_count) +{ + int i; + struct kms_atomic_desc *desc = crtc->state->desc; + + /* for active crtc do modeset on the native resolution */ + drmModeAtomicReq *req = drmModeAtomicAlloc(); + struct drm_mode_modeinfo *mode = crtc->mode.data; + struct kms_atomic_plane_state plane; + struct igt_fb fb; + + crtc_populate_req(crtc, req); + + /* Add plane data to the structure...*/ + uint32_t crtc_x = 0; + uint32_t crtc_y = 0; + + for (i = 0; i < plane_count; i++) { + plane = *plane_array[i]; + uint32_t format = plane_get_igt_format(&plane); + + igt_require(format != 0); + plane.src_x = 0; + plane.src_y = 0; + plane.src_w = (mode->hdisplay / (1)) << 16; + plane.crtc_x = crtc_x; + plane.crtc_y = crtc_y; + plane.crtc_w = (mode->hdisplay) / (1); + plane.crtc_h = (mode->vdisplay) / (i + 1); + + plane.crtc_id = crtc->obj; + + if (i%2 == 0) { + plane.src_h = (mode->vdisplay / (1)) << 16; + plane.crtc_h = (mode->vdisplay) / (1); + } + + if (i%2 == 1) { + plane.src_h = ceil((mode->vdisplay / 200) << 16); + plane.crtc_h = ceil((mode->vdisplay / 200)); + } + + plane.fb_id = igt_create_fb(plane.state->desc->fd, + plane.crtc_w, plane.crtc_h, + format, I915_TILING_NONE, &fb); + plane_populate_req(&plane, req); + } + do_atomic_commit(desc->fd, req, ATOMIC_RELAX_NONE); + drmModeAtomicFree(req); +} + + igt_main { struct kms_atomic_desc desc; @@ -1373,6 +1427,29 @@ igt_main atomic_state_free(scratch); } + igt_subtest("validate_dbuf") { + struct kms_atomic_state *scratch = atomic_state_dup(current); + struct kms_atomic_crtc_state *crtc = find_crtc(scratch, true); + struct kms_atomic_plane_state *plane; + struct kms_atomic_connector_state *connector = + find_connector(scratch, crtc); + struct kms_atomic_plane_state **plane_array = NULL; + /* Enabling Two planes */ + plane_array = calloc(2, sizeof(struct kms_atomic_plane_state *)); + int plane_count = 0; + + igt_require(crtc); + plane = find_plane(scratch, PLANE_TYPE_PRIMARY, crtc); + igt_require(plane); + plane_array[plane_count] = plane; plane_count++; + plane = find_plane(scratch, PLANE_TYPE_OVERLAY, crtc); + igt_require(plane); + plane_array[plane_count] = plane; plane_count++; + igt_require(connector); + validate_dbuf(crtc, plane_array, plane_count); + atomic_state_free(scratch); + } + atomic_state_free(current); igt_fixture