[02/19] drm/i915: Make INTEL_PCH_TYPE & co only take dev_priv

Commit Message

Tvrtko Ursulin Oct. 11, 2016, 1:21 p.m. UTC

From: Tvrtko Ursulin <[e-mail]>

This saves 1872 bytes of .rodata strings.

v2:
 * Rebase.
 * Add parantheses around dev_priv. (Ville Syrjala)

Signed-off-by: Tvrtko Ursulin <[e-mail]>
---
 drivers/gpu/drm/i915/i915_drv.h       | 16 ++++++------
 drivers/gpu/drm/i915/i915_gem.c       |  2 +-
 drivers/gpu/drm/i915/i915_gpu_error.c |  4 +--
 drivers/gpu/drm/i915/i915_irq.c       | 20 +++++++--------
 drivers/gpu/drm/i915/intel_audio.c    |  2 +-
 drivers/gpu/drm/i915/intel_crt.c      | 25 +++++++++---------
 drivers/gpu/drm/i915/intel_display.c  | 48 ++++++++++++++++++-----------------
 drivers/gpu/drm/i915/intel_dp.c       | 27 ++++++++++----------
 drivers/gpu/drm/i915/intel_dpll_mgr.c |  2 +-
 drivers/gpu/drm/i915/intel_hdmi.c     | 19 +++++++-------
 drivers/gpu/drm/i915/intel_i2c.c      |  2 +-
 drivers/gpu/drm/i915/intel_lvds.c     | 22 ++++++++--------
 drivers/gpu/drm/i915/intel_pm.c       |  6 ++---
 drivers/gpu/drm/i915/intel_sdvo.c     | 12 ++++-----
 14 files changed, 107 insertions(+), 100 deletions(-)

Comments

David Weinehall Oct. 12, 2016, 9:33 a.m. UTC | #1

On Tue, Oct 11, 2016 at 02:21:35PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin <[e-mail]>
> 
> This saves 1872 bytes of .rodata strings.
> 
> v2:
>  * Rebase.
>  * Add parantheses around dev_priv. (Ville Syrjala)
> 
> Signed-off-by: Tvrtko Ursulin <[e-mail]>

Reviewed-by: David Weinehall <[e-mail]>

> ---
>  drivers/gpu/drm/i915/i915_drv.h       | 16 ++++++------
>  drivers/gpu/drm/i915/i915_gem.c       |  2 +-
>  drivers/gpu/drm/i915/i915_gpu_error.c |  4 +--
>  drivers/gpu/drm/i915/i915_irq.c       | 20 +++++++--------
>  drivers/gpu/drm/i915/intel_audio.c    |  2 +-
>  drivers/gpu/drm/i915/intel_crt.c      | 25 +++++++++---------
>  drivers/gpu/drm/i915/intel_display.c  | 48 ++++++++++++++++++-----------------
>  drivers/gpu/drm/i915/intel_dp.c       | 27 ++++++++++----------
>  drivers/gpu/drm/i915/intel_dpll_mgr.c |  2 +-
>  drivers/gpu/drm/i915/intel_hdmi.c     | 19 +++++++-------
>  drivers/gpu/drm/i915/intel_i2c.c      |  2 +-
>  drivers/gpu/drm/i915/intel_lvds.c     | 22 ++++++++--------
>  drivers/gpu/drm/i915/intel_pm.c       |  6 ++---
>  drivers/gpu/drm/i915/intel_sdvo.c     | 12 ++++-----
>  14 files changed, 107 insertions(+), 100 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 51dd10f25f59..3caa1c767512 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2850,18 +2850,18 @@ struct drm_i915_cmd_table {
>  #define INTEL_PCH_P3X_DEVICE_ID_TYPE		0x7000
>  #define INTEL_PCH_QEMU_DEVICE_ID_TYPE		0x2900 /* qemu q35 has 2918 */
>  
> -#define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
> -#define HAS_PCH_KBP(dev) (INTEL_PCH_TYPE(dev) == PCH_KBP)
> -#define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
> -#define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
> +#define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
> +#define HAS_PCH_KBP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_KBP)
> +#define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT)
> +#define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT)
>  #define HAS_PCH_LPT_LP(dev_priv) \
>  	((dev_priv)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
>  #define HAS_PCH_LPT_H(dev_priv) \
>  	((dev_priv)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE)
> -#define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
> -#define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
> -#define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
> -#define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
> +#define HAS_PCH_CPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CPT)
> +#define HAS_PCH_IBX(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_IBX)
> +#define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP)
> +#define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE)
>  
>  #define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->has_gmch_display)
>  
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index fdd496e6c081..6b099f0198cc 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -4365,7 +4365,7 @@ i915_gem_init_hw(struct drm_device *dev)
>  		I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ?
>  			   LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
>  
> -	if (HAS_PCH_NOP(dev)) {
> +	if (HAS_PCH_NOP(dev_priv)) {
>  		if (IS_IVYBRIDGE(dev)) {
>  			u32 temp = I915_READ(GEN7_MSG_CTL);
>  			temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
> index b5b58692ac5a..d41517e11978 100644
> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> @@ -421,7 +421,7 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
>  		for (i = 0; i < 4; i++)
>  			err_printf(m, "GTIER gt %d: 0x%08x\n", i,
>  				   error->gtier[i]);
> -	} else if (HAS_PCH_SPLIT(dev) || IS_VALLEYVIEW(dev))
> +	} else if (HAS_PCH_SPLIT(dev_priv) || IS_VALLEYVIEW(dev_priv))
>  		err_printf(m, "GTIER: 0x%08x\n", error->gtier[0]);
>  	err_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er);
>  	err_printf(m, "FORCEWAKE: 0x%08x\n", error->forcewake);
> @@ -1393,7 +1393,7 @@ static void i915_capture_reg_state(struct drm_i915_private *dev_priv,
>  		error->ier = I915_READ(GEN8_DE_MISC_IER);
>  		for (i = 0; i < 4; i++)
>  			error->gtier[i] = I915_READ(GEN8_GT_IER(i));
> -	} else if (HAS_PCH_SPLIT(dev)) {
> +	} else if (HAS_PCH_SPLIT(dev_priv)) {
>  		error->ier = I915_READ(DEIER);
>  		error->gtier[0] = I915_READ(GTIER);
>  	} else if (IS_GEN2(dev)) {
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index bd6c8b0eeaef..883474411aee 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -3237,12 +3237,12 @@ static void ibx_irq_reset(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(dev);
>  
> -	if (HAS_PCH_NOP(dev))
> +	if (HAS_PCH_NOP(dev_priv))
>  		return;
>  
>  	GEN5_IRQ_RESET(SDE);
>  
> -	if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
> +	if (HAS_PCH_CPT(dev_priv) || HAS_PCH_LPT(dev_priv))
>  		I915_WRITE(SERR_INT, 0xffffffff);
>  }
>  
> @@ -3258,7 +3258,7 @@ static void ibx_irq_pre_postinstall(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(dev);
>  
> -	if (HAS_PCH_NOP(dev))
> +	if (HAS_PCH_NOP(dev_priv))
>  		return;
>  
>  	WARN_ON(I915_READ(SDEIER) != 0);
> @@ -3383,7 +3383,7 @@ static void gen8_irq_reset(struct drm_device *dev)
>  	GEN5_IRQ_RESET(GEN8_DE_MISC_);
>  	GEN5_IRQ_RESET(GEN8_PCU_);
>  
> -	if (HAS_PCH_SPLIT(dev))
> +	if (HAS_PCH_SPLIT(dev_priv))
>  		ibx_irq_reset(dev);
>  }
>  
> @@ -3572,10 +3572,10 @@ static void ibx_irq_postinstall(struct drm_device *dev)
>  	struct drm_i915_private *dev_priv = to_i915(dev);
>  	u32 mask;
>  
> -	if (HAS_PCH_NOP(dev))
> +	if (HAS_PCH_NOP(dev_priv))
>  		return;
>  
> -	if (HAS_PCH_IBX(dev))
> +	if (HAS_PCH_IBX(dev_priv))
>  		mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON;
>  	else
>  		mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
> @@ -3796,13 +3796,13 @@ static int gen8_irq_postinstall(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(dev);
>  
> -	if (HAS_PCH_SPLIT(dev))
> +	if (HAS_PCH_SPLIT(dev_priv))
>  		ibx_irq_pre_postinstall(dev);
>  
>  	gen8_gt_irq_postinstall(dev_priv);
>  	gen8_de_irq_postinstall(dev_priv);
>  
> -	if (HAS_PCH_SPLIT(dev))
> +	if (HAS_PCH_SPLIT(dev_priv))
>  		ibx_irq_postinstall(dev);
>  
>  	I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
> @@ -4599,11 +4599,11 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
>  		dev->driver->disable_vblank = gen8_disable_vblank;
>  		if (IS_BROXTON(dev))
>  			dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
> -		else if (HAS_PCH_SPT(dev) || HAS_PCH_KBP(dev))
> +		else if (HAS_PCH_SPT(dev_priv) || HAS_PCH_KBP(dev_priv))
>  			dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
>  		else
>  			dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
> -	} else if (HAS_PCH_SPLIT(dev)) {
> +	} else if (HAS_PCH_SPLIT(dev_priv)) {
>  		dev->driver->irq_handler = ironlake_irq_handler;
>  		dev->driver->irq_preinstall = ironlake_irq_reset;
>  		dev->driver->irq_postinstall = ironlake_irq_postinstall;
> diff --git a/drivers/gpu/drm/i915/intel_audio.c b/drivers/gpu/drm/i915/intel_audio.c
> index 9583f432e02e..13b726916f98 100644
> --- a/drivers/gpu/drm/i915/intel_audio.c
> +++ b/drivers/gpu/drm/i915/intel_audio.c
> @@ -423,7 +423,7 @@ static void ilk_audio_codec_enable(struct drm_connector *connector,
>  	 * infrastructure is not there yet.
>  	 */
>  
> -	if (HAS_PCH_IBX(connector->dev)) {
> +	if (HAS_PCH_IBX(dev_priv)) {
>  		hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
>  		aud_config = IBX_AUD_CFG(pipe);
>  		aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
> diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
> index d4b9b166de5d..f8919ef3a7af 100644
> --- a/drivers/gpu/drm/i915/intel_crt.c
> +++ b/drivers/gpu/drm/i915/intel_crt.c
> @@ -84,7 +84,7 @@ static bool intel_crt_get_hw_state(struct intel_encoder *encoder,
>  	if (!(tmp & ADPA_DAC_ENABLE))
>  		goto out;
>  
> -	if (HAS_PCH_CPT(dev))
> +	if (HAS_PCH_CPT(dev_priv))
>  		*pipe = PORT_TO_PIPE_CPT(tmp);
>  	else
>  		*pipe = PORT_TO_PIPE(tmp);
> @@ -165,16 +165,16 @@ static void intel_crt_set_dpms(struct intel_encoder *encoder,
>  		adpa |= ADPA_VSYNC_ACTIVE_HIGH;
>  
>  	/* For CPT allow 3 pipe config, for others just use A or B */
> -	if (HAS_PCH_LPT(dev))
> +	if (HAS_PCH_LPT(dev_priv))
>  		; /* Those bits don't exist here */
> -	else if (HAS_PCH_CPT(dev))
> +	else if (HAS_PCH_CPT(dev_priv))
>  		adpa |= PORT_TRANS_SEL_CPT(crtc->pipe);
>  	else if (crtc->pipe == 0)
>  		adpa |= ADPA_PIPE_A_SELECT;
>  	else
>  		adpa |= ADPA_PIPE_B_SELECT;
>  
> -	if (!HAS_PCH_SPLIT(dev))
> +	if (!HAS_PCH_SPLIT(dev_priv))
>  		I915_WRITE(BCLRPAT(crtc->pipe), 0);
>  
>  	switch (mode) {
> @@ -241,7 +241,8 @@ intel_crt_mode_valid(struct drm_connector *connector,
>  		     struct drm_display_mode *mode)
>  {
>  	struct drm_device *dev = connector->dev;
> -	int max_dotclk = to_i915(dev)->max_dotclk_freq;
> +	struct drm_i915_private *dev_priv = to_i915(dev);
> +	int max_dotclk = dev_priv->max_dotclk_freq;
>  	int max_clock;
>  
>  	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
> @@ -250,7 +251,7 @@ intel_crt_mode_valid(struct drm_connector *connector,
>  	if (mode->clock < 25000)
>  		return MODE_CLOCK_LOW;
>  
> -	if (HAS_PCH_LPT(dev))
> +	if (HAS_PCH_LPT(dev_priv))
>  		max_clock = 180000;
>  	else if (IS_VALLEYVIEW(dev))
>  		/*
> @@ -269,7 +270,7 @@ intel_crt_mode_valid(struct drm_connector *connector,
>  		return MODE_CLOCK_HIGH;
>  
>  	/* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */
> -	if (HAS_PCH_LPT(dev) &&
> +	if (HAS_PCH_LPT(dev_priv) &&
>  	    (ironlake_get_lanes_required(mode->clock, 270000, 24) > 2))
>  		return MODE_CLOCK_HIGH;
>  
> @@ -312,7 +313,7 @@ static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector)
>  
>  	/* The first time through, trigger an explicit detection cycle */
>  	if (crt->force_hotplug_required) {
> -		bool turn_off_dac = HAS_PCH_SPLIT(dev);
> +		bool turn_off_dac = HAS_PCH_SPLIT(dev_priv);
>  		u32 save_adpa;
>  
>  		crt->force_hotplug_required = 0;
> @@ -419,7 +420,7 @@ static bool intel_crt_detect_hotplug(struct drm_connector *connector)
>  	bool ret = false;
>  	int i, tries = 0;
>  
> -	if (HAS_PCH_SPLIT(dev))
> +	if (HAS_PCH_SPLIT(dev_priv))
>  		return intel_ironlake_crt_detect_hotplug(connector);
>  
>  	if (IS_VALLEYVIEW(dev))
> @@ -847,7 +848,7 @@ void intel_crt_init(struct drm_device *dev)
>  	i915_reg_t adpa_reg;
>  	u32 adpa;
>  
> -	if (HAS_PCH_SPLIT(dev))
> +	if (HAS_PCH_SPLIT(dev_priv))
>  		adpa_reg = PCH_ADPA;
>  	else if (IS_VALLEYVIEW(dev))
>  		adpa_reg = VLV_ADPA;
> @@ -907,7 +908,7 @@ void intel_crt_init(struct drm_device *dev)
>  	crt->adpa_reg = adpa_reg;
>  
>  	crt->base.compute_config = intel_crt_compute_config;
> -	if (HAS_PCH_SPLIT(dev)) {
> +	if (HAS_PCH_SPLIT(dev_priv)) {
>  		crt->base.disable = pch_disable_crt;
>  		crt->base.post_disable = pch_post_disable_crt;
>  	} else {
> @@ -944,7 +945,7 @@ void intel_crt_init(struct drm_device *dev)
>  	 * polarity and link reversal bits or not, instead of relying on the
>  	 * BIOS.
>  	 */
> -	if (HAS_PCH_LPT(dev)) {
> +	if (HAS_PCH_LPT(dev_priv)) {
>  		u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT |
>  				 FDI_RX_LINK_REVERSAL_OVERRIDE;
>  
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 6e447b575413..0a69e80821ee 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1784,7 +1784,6 @@ void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
>  static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
>  					   enum pipe pipe)
>  {
> -	struct drm_device *dev = &dev_priv->drm;
>  	struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
>  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>  	i915_reg_t reg;
> @@ -1797,7 +1796,7 @@ static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
>  	assert_fdi_tx_enabled(dev_priv, pipe);
>  	assert_fdi_rx_enabled(dev_priv, pipe);
>  
> -	if (HAS_PCH_CPT(dev)) {
> +	if (HAS_PCH_CPT(dev_priv)) {
>  		/* Workaround: Set the timing override bit before enabling the
>  		 * pch transcoder. */
>  		reg = TRANS_CHICKEN2(pipe);
> @@ -1875,7 +1874,6 @@ static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
>  static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
>  					    enum pipe pipe)
>  {
> -	struct drm_device *dev = &dev_priv->drm;
>  	i915_reg_t reg;
>  	uint32_t val;
>  
> @@ -1896,7 +1894,7 @@ static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
>  				    50))
>  		DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
>  
> -	if (HAS_PCH_CPT(dev)) {
> +	if (HAS_PCH_CPT(dev_priv)) {
>  		/* Workaround: Clear the timing override chicken bit again. */
>  		reg = TRANS_CHICKEN2(pipe);
>  		val = I915_READ(reg);
> @@ -3712,7 +3710,7 @@ static void intel_update_pipe_config(struct intel_crtc *crtc,
>  
>  		if (pipe_config->pch_pfit.enabled)
>  			skylake_pfit_enable(crtc);
> -	} else if (HAS_PCH_SPLIT(dev)) {
> +	} else if (HAS_PCH_SPLIT(dev_priv)) {
>  		if (pipe_config->pch_pfit.enabled)
>  			ironlake_pfit_enable(crtc);
>  		else if (old_crtc_state->pch_pfit.enabled)
> @@ -3743,7 +3741,7 @@ static void intel_fdi_normal_train(struct drm_crtc *crtc)
>  
>  	reg = FDI_RX_CTL(pipe);
>  	temp = I915_READ(reg);
> -	if (HAS_PCH_CPT(dev)) {
> +	if (HAS_PCH_CPT(dev_priv)) {
>  		temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
>  		temp |= FDI_LINK_TRAIN_NORMAL_CPT;
>  	} else {
> @@ -3901,7 +3899,7 @@ static void gen6_fdi_link_train(struct drm_crtc *crtc)
>  
>  	reg = FDI_RX_CTL(pipe);
>  	temp = I915_READ(reg);
> -	if (HAS_PCH_CPT(dev)) {
> +	if (HAS_PCH_CPT(dev_priv)) {
>  		temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
>  		temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
>  	} else {
> @@ -3954,7 +3952,7 @@ static void gen6_fdi_link_train(struct drm_crtc *crtc)
>  
>  	reg = FDI_RX_CTL(pipe);
>  	temp = I915_READ(reg);
> -	if (HAS_PCH_CPT(dev)) {
> +	if (HAS_PCH_CPT(dev_priv)) {
>  		temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
>  		temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
>  	} else {
> @@ -4208,7 +4206,7 @@ static void ironlake_fdi_disable(struct drm_crtc *crtc)
>  	udelay(100);
>  
>  	/* Ironlake workaround, disable clock pointer after downing FDI */
> -	if (HAS_PCH_IBX(dev))
> +	if (HAS_PCH_IBX(dev_priv))
>  		I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
>  
>  	/* still set train pattern 1 */
> @@ -4220,7 +4218,7 @@ static void ironlake_fdi_disable(struct drm_crtc *crtc)
>  
>  	reg = FDI_RX_CTL(pipe);
>  	temp = I915_READ(reg);
> -	if (HAS_PCH_CPT(dev)) {
> +	if (HAS_PCH_CPT(dev_priv)) {
>  		temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
>  		temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
>  	} else {
> @@ -4556,7 +4554,7 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
>  
>  	/* We need to program the right clock selection before writing the pixel
>  	 * mutliplier into the DPLL. */
> -	if (HAS_PCH_CPT(dev)) {
> +	if (HAS_PCH_CPT(dev_priv)) {
>  		u32 sel;
>  
>  		temp = I915_READ(PCH_DPLL_SEL);
> @@ -4586,7 +4584,8 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
>  	intel_fdi_normal_train(crtc);
>  
>  	/* For PCH DP, enable TRANS_DP_CTL */
> -	if (HAS_PCH_CPT(dev) && intel_crtc_has_dp_encoder(intel_crtc->config)) {
> +	if (HAS_PCH_CPT(dev_priv) &&
> +	    intel_crtc_has_dp_encoder(intel_crtc->config)) {
>  		const struct drm_display_mode *adjusted_mode =
>  			&intel_crtc->config->base.adjusted_mode;
>  		u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
> @@ -5380,7 +5379,7 @@ static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
>  
>  	intel_encoders_enable(crtc, pipe_config, old_state);
>  
> -	if (HAS_PCH_CPT(dev))
> +	if (HAS_PCH_CPT(dev_priv))
>  		cpt_verify_modeset(dev, intel_crtc->pipe);
>  
>  	/* Must wait for vblank to avoid spurious PCH FIFO underruns */
> @@ -5562,7 +5561,7 @@ static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
>  	if (intel_crtc->config->has_pch_encoder) {
>  		ironlake_disable_pch_transcoder(dev_priv, pipe);
>  
> -		if (HAS_PCH_CPT(dev)) {
> +		if (HAS_PCH_CPT(dev_priv)) {
>  			i915_reg_t reg;
>  			u32 temp;
>  
> @@ -8948,7 +8947,7 @@ static void ironlake_init_pch_refclk(struct drm_device *dev)
>  		}
>  	}
>  
> -	if (HAS_PCH_IBX(dev)) {
> +	if (HAS_PCH_IBX(dev_priv)) {
>  		has_ck505 = dev_priv->vbt.display_clock_mode;
>  		can_ssc = has_ck505;
>  	} else {
> @@ -9344,9 +9343,11 @@ static void lpt_init_pch_refclk(struct drm_device *dev)
>   */
>  void intel_init_pch_refclk(struct drm_device *dev)
>  {
> -	if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
> +	struct drm_i915_private *dev_priv = to_i915(dev);
> +
> +	if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
>  		ironlake_init_pch_refclk(dev);
> -	else if (HAS_PCH_LPT(dev))
> +	else if (HAS_PCH_LPT(dev_priv))
>  		lpt_init_pch_refclk(dev);
>  }
>  
> @@ -9475,7 +9476,7 @@ static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
>  	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
>  		if ((intel_panel_use_ssc(dev_priv) &&
>  		     dev_priv->vbt.lvds_ssc_freq == 100000) ||
> -		    (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
> +		    (HAS_PCH_IBX(dev_priv) && intel_is_dual_link_lvds(dev)))
>  			factor = 25;
>  	} else if (crtc_state->sdvo_tv_clock)
>  		factor = 20;
> @@ -11313,7 +11314,7 @@ static int i9xx_pll_refclk(struct drm_device *dev,
>  
>  	if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
>  		return dev_priv->vbt.lvds_ssc_freq;
> -	else if (HAS_PCH_SPLIT(dev))
> +	else if (HAS_PCH_SPLIT(dev_priv))
>  		return 120000;
>  	else if (!IS_GEN2(dev))
>  		return 96000;
> @@ -14898,6 +14899,7 @@ const struct drm_plane_funcs intel_plane_funcs = {
>  static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
>  						    int pipe)
>  {
> +	struct drm_i915_private *dev_priv = to_i915(dev);
>  	struct intel_plane *primary = NULL;
>  	struct intel_plane_state *state = NULL;
>  	const uint32_t *intel_primary_formats;
> @@ -14932,7 +14934,7 @@ static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
>  
>  		primary->update_plane = skylake_update_primary_plane;
>  		primary->disable_plane = skylake_disable_primary_plane;
> -	} else if (HAS_PCH_SPLIT(dev)) {
> +	} else if (HAS_PCH_SPLIT(dev_priv)) {
>  		intel_primary_formats = i965_primary_formats;
>  		num_formats = ARRAY_SIZE(i965_primary_formats);
>  
> @@ -15440,7 +15442,7 @@ static void intel_setup_outputs(struct drm_device *dev)
>  		     dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
>  			intel_ddi_init(dev, PORT_E);
>  
> -	} else if (HAS_PCH_SPLIT(dev)) {
> +	} else if (HAS_PCH_SPLIT(dev_priv)) {
>  		int found;
>  		dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
>  
> @@ -16359,7 +16361,7 @@ void intel_modeset_init(struct drm_device *dev)
>  	 * BIOS isn't using it, don't assume it will work even if the VBT
>  	 * indicates as much.
>  	 */
> -	if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
> +	if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
>  		bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
>  					    DREF_SSC1_ENABLE);
>  
> @@ -16908,7 +16910,7 @@ intel_modeset_setup_hw_state(struct drm_device *dev)
>  		vlv_wm_get_hw_state(dev);
>  	else if (IS_GEN9(dev))
>  		skl_wm_get_hw_state(dev);
> -	else if (HAS_PCH_SPLIT(dev))
> +	else if (HAS_PCH_SPLIT(dev_priv))
>  		ilk_wm_get_hw_state(dev);
>  
>  	for_each_intel_crtc(dev, crtc) {
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index edaf35b975c0..0b6f1bab671d 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1336,13 +1336,14 @@ intel_dp_set_clock(struct intel_encoder *encoder,
>  		   struct intel_crtc_state *pipe_config)
>  {
>  	struct drm_device *dev = encoder->base.dev;
> +	struct drm_i915_private *dev_priv = to_i915(dev);
>  	const struct dp_link_dpll *divisor = NULL;
>  	int i, count = 0;
>  
>  	if (IS_G4X(dev)) {
>  		divisor = gen4_dpll;
>  		count = ARRAY_SIZE(gen4_dpll);
> -	} else if (HAS_PCH_SPLIT(dev)) {
> +	} else if (HAS_PCH_SPLIT(dev_priv)) {
>  		divisor = pch_dpll;
>  		count = ARRAY_SIZE(pch_dpll);
>  	} else if (IS_CHERRYVIEW(dev)) {
> @@ -1776,7 +1777,7 @@ static void intel_dp_prepare(struct intel_encoder *encoder,
>  			intel_dp->DP |= DP_ENHANCED_FRAMING;
>  
>  		intel_dp->DP |= crtc->pipe << 29;
> -	} else if (HAS_PCH_CPT(dev) && port != PORT_A) {
> +	} else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
>  		u32 trans_dp;
>  
>  		intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
> @@ -1788,7 +1789,7 @@ static void intel_dp_prepare(struct intel_encoder *encoder,
>  			trans_dp &= ~TRANS_DP_ENH_FRAMING;
>  		I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
>  	} else {
> -		if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
> +		if (!HAS_PCH_SPLIT(dev_priv) && !IS_VALLEYVIEW(dev) &&
>  		    !IS_CHERRYVIEW(dev) && pipe_config->limited_color_range)
>  			intel_dp->DP |= DP_COLOR_RANGE_16_235;
>  
> @@ -2442,7 +2443,7 @@ static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
>  
>  	if (IS_GEN7(dev) && port == PORT_A) {
>  		*pipe = PORT_TO_PIPE_CPT(tmp);
> -	} else if (HAS_PCH_CPT(dev) && port != PORT_A) {
> +	} else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
>  		enum pipe p;
>  
>  		for_each_pipe(dev_priv, p) {
> @@ -2485,7 +2486,7 @@ static void intel_dp_get_config(struct intel_encoder *encoder,
>  
>  	pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
>  
> -	if (HAS_PCH_CPT(dev) && port != PORT_A) {
> +	if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
>  		u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
>  
>  		if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
> @@ -2511,8 +2512,8 @@ static void intel_dp_get_config(struct intel_encoder *encoder,
>  
>  	pipe_config->base.adjusted_mode.flags |= flags;
>  
> -	if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
> -	    !IS_CHERRYVIEW(dev) && tmp & DP_COLOR_RANGE_16_235)
> +	if (!HAS_PCH_SPLIT(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
> +	    !IS_CHERRYVIEW(dev_priv) && tmp & DP_COLOR_RANGE_16_235)
>  		pipe_config->limited_color_range = true;
>  
>  	pipe_config->lane_count =
> @@ -2659,7 +2660,7 @@ _intel_dp_set_link_train(struct intel_dp *intel_dp,
>  		I915_WRITE(DP_TP_CTL(port), temp);
>  
>  	} else if ((IS_GEN7(dev) && port == PORT_A) ||
> -		   (HAS_PCH_CPT(dev) && port != PORT_A)) {
> +		   (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
>  		*DP &= ~DP_LINK_TRAIN_MASK_CPT;
>  
>  		switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
> @@ -2989,7 +2990,7 @@ intel_dp_voltage_max(struct intel_dp *intel_dp)
>  		return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
>  	else if (IS_GEN7(dev) && port == PORT_A)
>  		return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
> -	else if (HAS_PCH_CPT(dev) && port != PORT_A)
> +	else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
>  		return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
>  	else
>  		return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
> @@ -3442,7 +3443,7 @@ intel_dp_link_down(struct intel_dp *intel_dp)
>  	DRM_DEBUG_KMS("\n");
>  
>  	if ((IS_GEN7(dev) && port == PORT_A) ||
> -	    (HAS_PCH_CPT(dev) && port != PORT_A)) {
> +	    (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
>  		DP &= ~DP_LINK_TRAIN_MASK_CPT;
>  		DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
>  	} else {
> @@ -3464,7 +3465,7 @@ intel_dp_link_down(struct intel_dp *intel_dp)
>  	 * to transcoder A after disabling it to allow the
>  	 * matching HDMI port to be enabled on transcoder A.
>  	 */
> -	if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B && port != PORT_A) {
> +	if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B && port != PORT_A) {
>  		/*
>  		 * We get CPU/PCH FIFO underruns on the other pipe when
>  		 * doing the workaround. Sweep them under the rug.
> @@ -5085,7 +5086,7 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
>  	 * power sequencer any more. */
>  	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
>  		port_sel = PANEL_PORT_SELECT_VLV(port);
> -	} else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
> +	} else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
>  		if (port == PORT_A)
>  			port_sel = PANEL_PORT_SELECT_DPA;
>  		else
> @@ -5649,7 +5650,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
>  		intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
>  	else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
>  		intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
> -	else if (HAS_PCH_SPLIT(dev))
> +	else if (HAS_PCH_SPLIT(dev_priv))
>  		intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
>  	else
>  		intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider;
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> index d0c59c1793ef..c37ce1263142 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> @@ -1857,7 +1857,7 @@ void intel_shared_dpll_init(struct drm_device *dev)
>  		dpll_mgr = &bxt_pll_mgr;
>  	else if (HAS_DDI(dev_priv))
>  		dpll_mgr = &hsw_pll_mgr;
> -	else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
> +	else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
>  		dpll_mgr = &pch_pll_mgr;
>  
>  	if (!dpll_mgr) {
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> index 09b2146f157f..397e10f4b6f0 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -864,7 +864,7 @@ static void intel_hdmi_prepare(struct intel_encoder *encoder)
>  	intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
>  
>  	hdmi_val = SDVO_ENCODING_HDMI;
> -	if (!HAS_PCH_SPLIT(dev) && crtc->config->limited_color_range)
> +	if (!HAS_PCH_SPLIT(dev_priv) && crtc->config->limited_color_range)
>  		hdmi_val |= HDMI_COLOR_RANGE_16_235;
>  	if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
>  		hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH;
> @@ -879,7 +879,7 @@ static void intel_hdmi_prepare(struct intel_encoder *encoder)
>  	if (crtc->config->has_hdmi_sink)
>  		hdmi_val |= HDMI_MODE_SELECT_HDMI;
>  
> -	if (HAS_PCH_CPT(dev))
> +	if (HAS_PCH_CPT(dev_priv))
>  		hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);
>  	else if (IS_CHERRYVIEW(dev))
>  		hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe);
> @@ -911,7 +911,7 @@ static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
>  	if (!(tmp & SDVO_ENABLE))
>  		goto out;
>  
> -	if (HAS_PCH_CPT(dev))
> +	if (HAS_PCH_CPT(dev_priv))
>  		*pipe = PORT_TO_PIPE_CPT(tmp);
>  	else if (IS_CHERRYVIEW(dev))
>  		*pipe = SDVO_PORT_TO_PIPE_CHV(tmp);
> @@ -956,7 +956,7 @@ static void intel_hdmi_get_config(struct intel_encoder *encoder,
>  	if (tmp & SDVO_AUDIO_ENABLE)
>  		pipe_config->has_audio = true;
>  
> -	if (!HAS_PCH_SPLIT(dev) &&
> +	if (!HAS_PCH_SPLIT(dev_priv) &&
>  	    tmp & HDMI_COLOR_RANGE_16_235)
>  		pipe_config->limited_color_range = true;
>  
> @@ -1141,7 +1141,7 @@ static void intel_disable_hdmi(struct intel_encoder *encoder,
>  	 * to transcoder A after disabling it to allow the
>  	 * matching DP port to be enabled on transcoder A.
>  	 */
> -	if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B) {
> +	if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) {
>  		/*
>  		 * We get CPU/PCH FIFO underruns on the other pipe when
>  		 * doing the workaround. Sweep them under the rug.
> @@ -1896,7 +1896,7 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
>  		intel_hdmi->write_infoframe = hsw_write_infoframe;
>  		intel_hdmi->set_infoframes = hsw_set_infoframes;
>  		intel_hdmi->infoframe_enabled = hsw_infoframe_enabled;
> -	} else if (HAS_PCH_IBX(dev)) {
> +	} else if (HAS_PCH_IBX(dev_priv)) {
>  		intel_hdmi->write_infoframe = ibx_write_infoframe;
>  		intel_hdmi->set_infoframes = ibx_set_infoframes;
>  		intel_hdmi->infoframe_enabled = ibx_infoframe_enabled;
> @@ -1929,6 +1929,7 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
>  void intel_hdmi_init(struct drm_device *dev,
>  		     i915_reg_t hdmi_reg, enum port port)
>  {
> +	struct drm_i915_private *dev_priv = to_i915(dev);
>  	struct intel_digital_port *intel_dig_port;
>  	struct intel_encoder *intel_encoder;
>  	struct intel_connector *intel_connector;
> @@ -1949,7 +1950,7 @@ void intel_hdmi_init(struct drm_device *dev,
>  			 DRM_MODE_ENCODER_TMDS, "HDMI %c", port_name(port));
>  
>  	intel_encoder->compute_config = intel_hdmi_compute_config;
> -	if (HAS_PCH_SPLIT(dev)) {
> +	if (HAS_PCH_SPLIT(dev_priv)) {
>  		intel_encoder->disable = pch_disable_hdmi;
>  		intel_encoder->post_disable = pch_post_disable_hdmi;
>  	} else {
> @@ -1970,9 +1971,9 @@ void intel_hdmi_init(struct drm_device *dev,
>  		intel_encoder->post_disable = vlv_hdmi_post_disable;
>  	} else {
>  		intel_encoder->pre_enable = intel_hdmi_pre_enable;
> -		if (HAS_PCH_CPT(dev))
> +		if (HAS_PCH_CPT(dev_priv))
>  			intel_encoder->enable = cpt_enable_hdmi;
> -		else if (HAS_PCH_IBX(dev))
> +		else if (HAS_PCH_IBX(dev_priv))
>  			intel_encoder->enable = ibx_enable_hdmi;
>  		else
>  			intel_encoder->enable = g4x_enable_hdmi;
> diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
> index 79aab9ad6faa..1410330ec9bb 100644
> --- a/drivers/gpu/drm/i915/intel_i2c.c
> +++ b/drivers/gpu/drm/i915/intel_i2c.c
> @@ -633,7 +633,7 @@ int intel_setup_gmbus(struct drm_device *dev)
>  	unsigned int pin;
>  	int ret;
>  
> -	if (HAS_PCH_NOP(dev))
> +	if (HAS_PCH_NOP(dev_priv))
>  		return 0;
>  
>  	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
> diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
> index 2e943bd1c3cf..baaf2ed897ef 100644
> --- a/drivers/gpu/drm/i915/intel_lvds.c
> +++ b/drivers/gpu/drm/i915/intel_lvds.c
> @@ -106,7 +106,7 @@ static bool intel_lvds_get_hw_state(struct intel_encoder *encoder,
>  	if (!(tmp & LVDS_PORT_EN))
>  		goto out;
>  
> -	if (HAS_PCH_CPT(dev))
> +	if (HAS_PCH_CPT(dev_priv))
>  		*pipe = PORT_TO_PIPE_CPT(tmp);
>  	else
>  		*pipe = PORT_TO_PIPE(tmp);
> @@ -396,7 +396,7 @@ static bool intel_lvds_compute_config(struct intel_encoder *intel_encoder,
>  				      struct intel_crtc_state *pipe_config,
>  				      struct drm_connector_state *conn_state)
>  {
> -	struct drm_device *dev = intel_encoder->base.dev;
> +	struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
>  	struct intel_lvds_encoder *lvds_encoder =
>  		to_lvds_encoder(&intel_encoder->base);
>  	struct intel_connector *intel_connector =
> @@ -406,7 +406,7 @@ static bool intel_lvds_compute_config(struct intel_encoder *intel_encoder,
>  	unsigned int lvds_bpp;
>  
>  	/* Should never happen!! */
> -	if (INTEL_INFO(dev)->gen < 4 && intel_crtc->pipe == 0) {
> +	if (INTEL_GEN(dev_priv) < 4 && intel_crtc->pipe == 0) {
>  		DRM_ERROR("Can't support LVDS on pipe A\n");
>  		return false;
>  	}
> @@ -431,7 +431,7 @@ static bool intel_lvds_compute_config(struct intel_encoder *intel_encoder,
>  	intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
>  			       adjusted_mode);
>  
> -	if (HAS_PCH_SPLIT(dev)) {
> +	if (HAS_PCH_SPLIT(dev_priv)) {
>  		pipe_config->has_pch_encoder = true;
>  
>  		intel_pch_panel_fitting(intel_crtc, pipe_config,
> @@ -566,7 +566,7 @@ static int intel_lid_notify(struct notifier_block *nb, unsigned long val,
>  	 * and as part of the cleanup in the hw state restore we also redisable
>  	 * the vga plane.
>  	 */
> -	if (!HAS_PCH_SPLIT(dev))
> +	if (!HAS_PCH_SPLIT(dev_priv))
>  		intel_display_resume(dev);
>  
>  	dev_priv->modeset_restore = MODESET_DONE;
> @@ -951,9 +951,11 @@ static bool compute_is_dual_link_lvds(struct intel_lvds_encoder *lvds_encoder)
>  
>  static bool intel_lvds_supported(struct drm_device *dev)
>  {
> +	struct drm_i915_private *dev_priv = to_i915(dev);
> +
>  	/* With the introduction of the PCH we gained a dedicated
>  	 * LVDS presence pin, use it. */
> -	if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
> +	if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
>  		return true;
>  
>  	/* Otherwise LVDS was only attached to mobile products,
> @@ -997,14 +999,14 @@ void intel_lvds_init(struct drm_device *dev)
>  	if (dmi_check_system(intel_no_lvds))
>  		return;
>  
> -	if (HAS_PCH_SPLIT(dev))
> +	if (HAS_PCH_SPLIT(dev_priv))
>  		lvds_reg = PCH_LVDS;
>  	else
>  		lvds_reg = LVDS;
>  
>  	lvds = I915_READ(lvds_reg);
>  
> -	if (HAS_PCH_SPLIT(dev)) {
> +	if (HAS_PCH_SPLIT(dev_priv)) {
>  		if ((lvds & LVDS_DETECTED) == 0)
>  			return;
>  		if (dev_priv->vbt.edp.support) {
> @@ -1068,7 +1070,7 @@ void intel_lvds_init(struct drm_device *dev)
>  	intel_encoder->type = INTEL_OUTPUT_LVDS;
>  	intel_encoder->port = PORT_NONE;
>  	intel_encoder->cloneable = 0;
> -	if (HAS_PCH_SPLIT(dev))
> +	if (HAS_PCH_SPLIT(dev_priv))
>  		intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
>  	else if (IS_GEN4(dev))
>  		intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
> @@ -1158,7 +1160,7 @@ void intel_lvds_init(struct drm_device *dev)
>  	 */
>  
>  	/* Ironlake: FIXME if still fail, not try pipe mode now */
> -	if (HAS_PCH_SPLIT(dev))
> +	if (HAS_PCH_SPLIT(dev_priv))
>  		goto failed;
>  
>  	pipe = (lvds & LVDS_PIPEB_SELECT) ? 1 : 0;
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index e7b3e6f39281..86051ef2716e 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -7413,7 +7413,7 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
>  	snpcr |= GEN6_MBC_SNPCR_MED;
>  	I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
>  
> -	if (!HAS_PCH_NOP(dev))
> +	if (!HAS_PCH_NOP(dev_priv))
>  		cpt_init_clock_gating(dev);
>  
>  	gen6_check_mch_setup(dev);
> @@ -7656,7 +7656,7 @@ void intel_init_clock_gating(struct drm_device *dev)
>  
>  void intel_suspend_hw(struct drm_device *dev)
>  {
> -	if (HAS_PCH_LPT(dev))
> +	if (HAS_PCH_LPT(to_i915(dev)))
>  		lpt_suspend_hw(dev);
>  }
>  
> @@ -7732,7 +7732,7 @@ void intel_init_pm(struct drm_device *dev)
>  		skl_setup_wm_latency(dev);
>  		dev_priv->display.update_wm = skl_update_wm;
>  		dev_priv->display.compute_global_watermarks = skl_compute_wm;
> -	} else if (HAS_PCH_SPLIT(dev)) {
> +	} else if (HAS_PCH_SPLIT(dev_priv)) {
>  		ilk_setup_wm_latency(dev);
>  
>  		if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
> diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
> index a061b0029797..0d9114f9ce27 100644
> --- a/drivers/gpu/drm/i915/intel_sdvo.c
> +++ b/drivers/gpu/drm/i915/intel_sdvo.c
> @@ -251,7 +251,7 @@ static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val)
>  		 * HW workaround, need to write this twice for issue
>  		 * that may result in first write getting masked.
>  		 */
> -		if (HAS_PCH_IBX(dev)) {
> +		if (HAS_PCH_IBX(dev_priv)) {
>  			I915_WRITE(intel_sdvo->sdvo_reg, val);
>  			POSTING_READ(intel_sdvo->sdvo_reg);
>  		}
> @@ -1133,7 +1133,7 @@ static bool intel_sdvo_compute_config(struct intel_encoder *encoder,
>  	DRM_DEBUG_KMS("forcing bpc to 8 for SDVO\n");
>  	pipe_config->pipe_bpp = 8*3;
>  
> -	if (HAS_PCH_SPLIT(encoder->base.dev))
> +	if (HAS_PCH_SPLIT(to_i915(encoder->base.dev)))
>  		pipe_config->has_pch_encoder = true;
>  
>  	/* We need to construct preferred input timings based on our
> @@ -1273,7 +1273,7 @@ static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder,
>  		/* The real mode polarity is set by the SDVO commands, using
>  		 * struct intel_sdvo_dtd. */
>  		sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH;
> -		if (!HAS_PCH_SPLIT(dev) && crtc_state->limited_color_range)
> +		if (!HAS_PCH_SPLIT(dev_priv) && crtc_state->limited_color_range)
>  			sdvox |= HDMI_COLOR_RANGE_16_235;
>  		if (INTEL_INFO(dev)->gen < 5)
>  			sdvox |= SDVO_BORDER_ENABLE;
> @@ -1286,7 +1286,7 @@ static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder,
>  		sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
>  	}
>  
> -	if (INTEL_PCH_TYPE(dev) >= PCH_CPT)
> +	if (INTEL_PCH_TYPE(dev_priv) >= PCH_CPT)
>  		sdvox |= SDVO_PIPE_SEL_CPT(crtc->pipe);
>  	else
>  		sdvox |= SDVO_PIPE_SEL(crtc->pipe);
> @@ -1339,7 +1339,7 @@ static bool intel_sdvo_get_hw_state(struct intel_encoder *encoder,
>  	if (!(tmp & SDVO_ENABLE) && (active_outputs == 0))
>  		return false;
>  
> -	if (HAS_PCH_CPT(dev))
> +	if (HAS_PCH_CPT(dev_priv))
>  		*pipe = PORT_TO_PIPE_CPT(tmp);
>  	else
>  		*pipe = PORT_TO_PIPE(tmp);
> @@ -2997,7 +2997,7 @@ bool intel_sdvo_init(struct drm_device *dev,
>  	}
>  
>  	intel_encoder->compute_config = intel_sdvo_compute_config;
> -	if (HAS_PCH_SPLIT(dev)) {
> +	if (HAS_PCH_SPLIT(dev_priv)) {
>  		intel_encoder->disable = pch_disable_sdvo;
>  		intel_encoder->post_disable = pch_post_disable_sdvo;
>  	} else {
> -- 
> 2.7.4
> 
> _______________________________________________
> Intel-gfx mailing list
> [e-mail]
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Patch

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 51dd10f25f59..3caa1c767512 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2850,18 +2850,18 @@  struct drm_i915_cmd_table {
 #define INTEL_PCH_P3X_DEVICE_ID_TYPE		0x7000
 #define INTEL_PCH_QEMU_DEVICE_ID_TYPE		0x2900 /* qemu q35 has 2918 */
 
-#define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
-#define HAS_PCH_KBP(dev) (INTEL_PCH_TYPE(dev) == PCH_KBP)
-#define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
-#define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
+#define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
+#define HAS_PCH_KBP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_KBP)
+#define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT)
+#define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT)
 #define HAS_PCH_LPT_LP(dev_priv) \
 	((dev_priv)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
 #define HAS_PCH_LPT_H(dev_priv) \
 	((dev_priv)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE)
-#define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
-#define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
-#define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
-#define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
+#define HAS_PCH_CPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CPT)
+#define HAS_PCH_IBX(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_IBX)
+#define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP)
+#define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE)
 
 #define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->has_gmch_display)
 
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index fdd496e6c081..6b099f0198cc 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4365,7 +4365,7 @@  i915_gem_init_hw(struct drm_device *dev)
 		I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ?
 			   LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
 
-	if (HAS_PCH_NOP(dev)) {
+	if (HAS_PCH_NOP(dev_priv)) {
 		if (IS_IVYBRIDGE(dev)) {
 			u32 temp = I915_READ(GEN7_MSG_CTL);
 			temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index b5b58692ac5a..d41517e11978 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -421,7 +421,7 @@  int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
 		for (i = 0; i < 4; i++)
 			err_printf(m, "GTIER gt %d: 0x%08x\n", i,
 				   error->gtier[i]);
-	} else if (HAS_PCH_SPLIT(dev) || IS_VALLEYVIEW(dev))
+	} else if (HAS_PCH_SPLIT(dev_priv) || IS_VALLEYVIEW(dev_priv))
 		err_printf(m, "GTIER: 0x%08x\n", error->gtier[0]);
 	err_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er);
 	err_printf(m, "FORCEWAKE: 0x%08x\n", error->forcewake);
@@ -1393,7 +1393,7 @@  static void i915_capture_reg_state(struct drm_i915_private *dev_priv,
 		error->ier = I915_READ(GEN8_DE_MISC_IER);
 		for (i = 0; i < 4; i++)
 			error->gtier[i] = I915_READ(GEN8_GT_IER(i));
-	} else if (HAS_PCH_SPLIT(dev)) {
+	} else if (HAS_PCH_SPLIT(dev_priv)) {
 		error->ier = I915_READ(DEIER);
 		error->gtier[0] = I915_READ(GTIER);
 	} else if (IS_GEN2(dev)) {
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index bd6c8b0eeaef..883474411aee 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3237,12 +3237,12 @@  static void ibx_irq_reset(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = to_i915(dev);
 
-	if (HAS_PCH_NOP(dev))
+	if (HAS_PCH_NOP(dev_priv))
 		return;
 
 	GEN5_IRQ_RESET(SDE);
 
-	if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
+	if (HAS_PCH_CPT(dev_priv) || HAS_PCH_LPT(dev_priv))
 		I915_WRITE(SERR_INT, 0xffffffff);
 }
 
@@ -3258,7 +3258,7 @@  static void ibx_irq_pre_postinstall(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = to_i915(dev);
 
-	if (HAS_PCH_NOP(dev))
+	if (HAS_PCH_NOP(dev_priv))
 		return;
 
 	WARN_ON(I915_READ(SDEIER) != 0);
@@ -3383,7 +3383,7 @@  static void gen8_irq_reset(struct drm_device *dev)
 	GEN5_IRQ_RESET(GEN8_DE_MISC_);
 	GEN5_IRQ_RESET(GEN8_PCU_);
 
-	if (HAS_PCH_SPLIT(dev))
+	if (HAS_PCH_SPLIT(dev_priv))
 		ibx_irq_reset(dev);
 }
 
@@ -3572,10 +3572,10 @@  static void ibx_irq_postinstall(struct drm_device *dev)
 	struct drm_i915_private *dev_priv = to_i915(dev);
 	u32 mask;
 
-	if (HAS_PCH_NOP(dev))
+	if (HAS_PCH_NOP(dev_priv))
 		return;
 
-	if (HAS_PCH_IBX(dev))
+	if (HAS_PCH_IBX(dev_priv))
 		mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON;
 	else
 		mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
@@ -3796,13 +3796,13 @@  static int gen8_irq_postinstall(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = to_i915(dev);
 
-	if (HAS_PCH_SPLIT(dev))
+	if (HAS_PCH_SPLIT(dev_priv))
 		ibx_irq_pre_postinstall(dev);
 
 	gen8_gt_irq_postinstall(dev_priv);
 	gen8_de_irq_postinstall(dev_priv);
 
-	if (HAS_PCH_SPLIT(dev))
+	if (HAS_PCH_SPLIT(dev_priv))
 		ibx_irq_postinstall(dev);
 
 	I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
@@ -4599,11 +4599,11 @@  void intel_irq_init(struct drm_i915_private *dev_priv)
 		dev->driver->disable_vblank = gen8_disable_vblank;
 		if (IS_BROXTON(dev))
 			dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
-		else if (HAS_PCH_SPT(dev) || HAS_PCH_KBP(dev))
+		else if (HAS_PCH_SPT(dev_priv) || HAS_PCH_KBP(dev_priv))
 			dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
 		else
 			dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
-	} else if (HAS_PCH_SPLIT(dev)) {
+	} else if (HAS_PCH_SPLIT(dev_priv)) {
 		dev->driver->irq_handler = ironlake_irq_handler;
 		dev->driver->irq_preinstall = ironlake_irq_reset;
 		dev->driver->irq_postinstall = ironlake_irq_postinstall;
diff --git a/drivers/gpu/drm/i915/intel_audio.c b/drivers/gpu/drm/i915/intel_audio.c
index 9583f432e02e..13b726916f98 100644
--- a/drivers/gpu/drm/i915/intel_audio.c
+++ b/drivers/gpu/drm/i915/intel_audio.c
@@ -423,7 +423,7 @@  static void ilk_audio_codec_enable(struct drm_connector *connector,
 	 * infrastructure is not there yet.
 	 */
 
-	if (HAS_PCH_IBX(connector->dev)) {
+	if (HAS_PCH_IBX(dev_priv)) {
 		hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
 		aud_config = IBX_AUD_CFG(pipe);
 		aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index d4b9b166de5d..f8919ef3a7af 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -84,7 +84,7 @@  static bool intel_crt_get_hw_state(struct intel_encoder *encoder,
 	if (!(tmp & ADPA_DAC_ENABLE))
 		goto out;
 
-	if (HAS_PCH_CPT(dev))
+	if (HAS_PCH_CPT(dev_priv))
 		*pipe = PORT_TO_PIPE_CPT(tmp);
 	else
 		*pipe = PORT_TO_PIPE(tmp);
@@ -165,16 +165,16 @@  static void intel_crt_set_dpms(struct intel_encoder *encoder,
 		adpa |= ADPA_VSYNC_ACTIVE_HIGH;
 
 	/* For CPT allow 3 pipe config, for others just use A or B */
-	if (HAS_PCH_LPT(dev))
+	if (HAS_PCH_LPT(dev_priv))
 		; /* Those bits don't exist here */
-	else if (HAS_PCH_CPT(dev))
+	else if (HAS_PCH_CPT(dev_priv))
 		adpa |= PORT_TRANS_SEL_CPT(crtc->pipe);
 	else if (crtc->pipe == 0)
 		adpa |= ADPA_PIPE_A_SELECT;
 	else
 		adpa |= ADPA_PIPE_B_SELECT;
 
-	if (!HAS_PCH_SPLIT(dev))
+	if (!HAS_PCH_SPLIT(dev_priv))
 		I915_WRITE(BCLRPAT(crtc->pipe), 0);
 
 	switch (mode) {
@@ -241,7 +241,8 @@  intel_crt_mode_valid(struct drm_connector *connector,
 		     struct drm_display_mode *mode)
 {
 	struct drm_device *dev = connector->dev;
-	int max_dotclk = to_i915(dev)->max_dotclk_freq;
+	struct drm_i915_private *dev_priv = to_i915(dev);
+	int max_dotclk = dev_priv->max_dotclk_freq;
 	int max_clock;
 
 	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
@@ -250,7 +251,7 @@  intel_crt_mode_valid(struct drm_connector *connector,
 	if (mode->clock < 25000)
 		return MODE_CLOCK_LOW;
 
-	if (HAS_PCH_LPT(dev))
+	if (HAS_PCH_LPT(dev_priv))
 		max_clock = 180000;
 	else if (IS_VALLEYVIEW(dev))
 		/*
@@ -269,7 +270,7 @@  intel_crt_mode_valid(struct drm_connector *connector,
 		return MODE_CLOCK_HIGH;
 
 	/* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */
-	if (HAS_PCH_LPT(dev) &&
+	if (HAS_PCH_LPT(dev_priv) &&
 	    (ironlake_get_lanes_required(mode->clock, 270000, 24) > 2))
 		return MODE_CLOCK_HIGH;
 
@@ -312,7 +313,7 @@  static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector)
 
 	/* The first time through, trigger an explicit detection cycle */
 	if (crt->force_hotplug_required) {
-		bool turn_off_dac = HAS_PCH_SPLIT(dev);
+		bool turn_off_dac = HAS_PCH_SPLIT(dev_priv);
 		u32 save_adpa;
 
 		crt->force_hotplug_required = 0;
@@ -419,7 +420,7 @@  static bool intel_crt_detect_hotplug(struct drm_connector *connector)
 	bool ret = false;
 	int i, tries = 0;
 
-	if (HAS_PCH_SPLIT(dev))
+	if (HAS_PCH_SPLIT(dev_priv))
 		return intel_ironlake_crt_detect_hotplug(connector);
 
 	if (IS_VALLEYVIEW(dev))
@@ -847,7 +848,7 @@  void intel_crt_init(struct drm_device *dev)
 	i915_reg_t adpa_reg;
 	u32 adpa;
 
-	if (HAS_PCH_SPLIT(dev))
+	if (HAS_PCH_SPLIT(dev_priv))
 		adpa_reg = PCH_ADPA;
 	else if (IS_VALLEYVIEW(dev))
 		adpa_reg = VLV_ADPA;
@@ -907,7 +908,7 @@  void intel_crt_init(struct drm_device *dev)
 	crt->adpa_reg = adpa_reg;
 
 	crt->base.compute_config = intel_crt_compute_config;
-	if (HAS_PCH_SPLIT(dev)) {
+	if (HAS_PCH_SPLIT(dev_priv)) {
 		crt->base.disable = pch_disable_crt;
 		crt->base.post_disable = pch_post_disable_crt;
 	} else {
@@ -944,7 +945,7 @@  void intel_crt_init(struct drm_device *dev)
 	 * polarity and link reversal bits or not, instead of relying on the
 	 * BIOS.
 	 */
-	if (HAS_PCH_LPT(dev)) {
+	if (HAS_PCH_LPT(dev_priv)) {
 		u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT |
 				 FDI_RX_LINK_REVERSAL_OVERRIDE;
 
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 6e447b575413..0a69e80821ee 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1784,7 +1784,6 @@  void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
 					   enum pipe pipe)
 {
-	struct drm_device *dev = &dev_priv->drm;
 	struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	i915_reg_t reg;
@@ -1797,7 +1796,7 @@  static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
 	assert_fdi_tx_enabled(dev_priv, pipe);
 	assert_fdi_rx_enabled(dev_priv, pipe);
 
-	if (HAS_PCH_CPT(dev)) {
+	if (HAS_PCH_CPT(dev_priv)) {
 		/* Workaround: Set the timing override bit before enabling the
 		 * pch transcoder. */
 		reg = TRANS_CHICKEN2(pipe);
@@ -1875,7 +1874,6 @@  static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
 					    enum pipe pipe)
 {
-	struct drm_device *dev = &dev_priv->drm;
 	i915_reg_t reg;
 	uint32_t val;
 
@@ -1896,7 +1894,7 @@  static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
 				    50))
 		DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
 
-	if (HAS_PCH_CPT(dev)) {
+	if (HAS_PCH_CPT(dev_priv)) {
 		/* Workaround: Clear the timing override chicken bit again. */
 		reg = TRANS_CHICKEN2(pipe);
 		val = I915_READ(reg);
@@ -3712,7 +3710,7 @@  static void intel_update_pipe_config(struct intel_crtc *crtc,
 
 		if (pipe_config->pch_pfit.enabled)
 			skylake_pfit_enable(crtc);
-	} else if (HAS_PCH_SPLIT(dev)) {
+	} else if (HAS_PCH_SPLIT(dev_priv)) {
 		if (pipe_config->pch_pfit.enabled)
 			ironlake_pfit_enable(crtc);
 		else if (old_crtc_state->pch_pfit.enabled)
@@ -3743,7 +3741,7 @@  static void intel_fdi_normal_train(struct drm_crtc *crtc)
 
 	reg = FDI_RX_CTL(pipe);
 	temp = I915_READ(reg);
-	if (HAS_PCH_CPT(dev)) {
+	if (HAS_PCH_CPT(dev_priv)) {
 		temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
 		temp |= FDI_LINK_TRAIN_NORMAL_CPT;
 	} else {
@@ -3901,7 +3899,7 @@  static void gen6_fdi_link_train(struct drm_crtc *crtc)
 
 	reg = FDI_RX_CTL(pipe);
 	temp = I915_READ(reg);
-	if (HAS_PCH_CPT(dev)) {
+	if (HAS_PCH_CPT(dev_priv)) {
 		temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
 		temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
 	} else {
@@ -3954,7 +3952,7 @@  static void gen6_fdi_link_train(struct drm_crtc *crtc)
 
 	reg = FDI_RX_CTL(pipe);
 	temp = I915_READ(reg);
-	if (HAS_PCH_CPT(dev)) {
+	if (HAS_PCH_CPT(dev_priv)) {
 		temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
 		temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
 	} else {
@@ -4208,7 +4206,7 @@  static void ironlake_fdi_disable(struct drm_crtc *crtc)
 	udelay(100);
 
 	/* Ironlake workaround, disable clock pointer after downing FDI */
-	if (HAS_PCH_IBX(dev))
+	if (HAS_PCH_IBX(dev_priv))
 		I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
 
 	/* still set train pattern 1 */
@@ -4220,7 +4218,7 @@  static void ironlake_fdi_disable(struct drm_crtc *crtc)
 
 	reg = FDI_RX_CTL(pipe);
 	temp = I915_READ(reg);
-	if (HAS_PCH_CPT(dev)) {
+	if (HAS_PCH_CPT(dev_priv)) {
 		temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
 		temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
 	} else {
@@ -4556,7 +4554,7 @@  static void ironlake_pch_enable(struct drm_crtc *crtc)
 
 	/* We need to program the right clock selection before writing the pixel
 	 * mutliplier into the DPLL. */
-	if (HAS_PCH_CPT(dev)) {
+	if (HAS_PCH_CPT(dev_priv)) {
 		u32 sel;
 
 		temp = I915_READ(PCH_DPLL_SEL);
@@ -4586,7 +4584,8 @@  static void ironlake_pch_enable(struct drm_crtc *crtc)
 	intel_fdi_normal_train(crtc);
 
 	/* For PCH DP, enable TRANS_DP_CTL */
-	if (HAS_PCH_CPT(dev) && intel_crtc_has_dp_encoder(intel_crtc->config)) {
+	if (HAS_PCH_CPT(dev_priv) &&
+	    intel_crtc_has_dp_encoder(intel_crtc->config)) {
 		const struct drm_display_mode *adjusted_mode =
 			&intel_crtc->config->base.adjusted_mode;
 		u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
@@ -5380,7 +5379,7 @@  static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
 
 	intel_encoders_enable(crtc, pipe_config, old_state);
 
-	if (HAS_PCH_CPT(dev))
+	if (HAS_PCH_CPT(dev_priv))
 		cpt_verify_modeset(dev, intel_crtc->pipe);
 
 	/* Must wait for vblank to avoid spurious PCH FIFO underruns */
@@ -5562,7 +5561,7 @@  static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
 	if (intel_crtc->config->has_pch_encoder) {
 		ironlake_disable_pch_transcoder(dev_priv, pipe);
 
-		if (HAS_PCH_CPT(dev)) {
+		if (HAS_PCH_CPT(dev_priv)) {
 			i915_reg_t reg;
 			u32 temp;
 
@@ -8948,7 +8947,7 @@  static void ironlake_init_pch_refclk(struct drm_device *dev)
 		}
 	}
 
-	if (HAS_PCH_IBX(dev)) {
+	if (HAS_PCH_IBX(dev_priv)) {
 		has_ck505 = dev_priv->vbt.display_clock_mode;
 		can_ssc = has_ck505;
 	} else {
@@ -9344,9 +9343,11 @@  static void lpt_init_pch_refclk(struct drm_device *dev)
  */
 void intel_init_pch_refclk(struct drm_device *dev)
 {
-	if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
+	struct drm_i915_private *dev_priv = to_i915(dev);
+
+	if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
 		ironlake_init_pch_refclk(dev);
-	else if (HAS_PCH_LPT(dev))
+	else if (HAS_PCH_LPT(dev_priv))
 		lpt_init_pch_refclk(dev);
 }
 
@@ -9475,7 +9476,7 @@  static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
 	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 		if ((intel_panel_use_ssc(dev_priv) &&
 		     dev_priv->vbt.lvds_ssc_freq == 100000) ||
-		    (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
+		    (HAS_PCH_IBX(dev_priv) && intel_is_dual_link_lvds(dev)))
 			factor = 25;
 	} else if (crtc_state->sdvo_tv_clock)
 		factor = 20;
@@ -11313,7 +11314,7 @@  static int i9xx_pll_refclk(struct drm_device *dev,
 
 	if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
 		return dev_priv->vbt.lvds_ssc_freq;
-	else if (HAS_PCH_SPLIT(dev))
+	else if (HAS_PCH_SPLIT(dev_priv))
 		return 120000;
 	else if (!IS_GEN2(dev))
 		return 96000;
@@ -14898,6 +14899,7 @@  const struct drm_plane_funcs intel_plane_funcs = {
 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
 						    int pipe)
 {
+	struct drm_i915_private *dev_priv = to_i915(dev);
 	struct intel_plane *primary = NULL;
 	struct intel_plane_state *state = NULL;
 	const uint32_t *intel_primary_formats;
@@ -14932,7 +14934,7 @@  static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
 
 		primary->update_plane = skylake_update_primary_plane;
 		primary->disable_plane = skylake_disable_primary_plane;
-	} else if (HAS_PCH_SPLIT(dev)) {
+	} else if (HAS_PCH_SPLIT(dev_priv)) {
 		intel_primary_formats = i965_primary_formats;
 		num_formats = ARRAY_SIZE(i965_primary_formats);
 
@@ -15440,7 +15442,7 @@  static void intel_setup_outputs(struct drm_device *dev)
 		     dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
 			intel_ddi_init(dev, PORT_E);
 
-	} else if (HAS_PCH_SPLIT(dev)) {
+	} else if (HAS_PCH_SPLIT(dev_priv)) {
 		int found;
 		dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
 
@@ -16359,7 +16361,7 @@  void intel_modeset_init(struct drm_device *dev)
 	 * BIOS isn't using it, don't assume it will work even if the VBT
 	 * indicates as much.
 	 */
-	if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
+	if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
 		bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
 					    DREF_SSC1_ENABLE);
 
@@ -16908,7 +16910,7 @@  intel_modeset_setup_hw_state(struct drm_device *dev)
 		vlv_wm_get_hw_state(dev);
 	else if (IS_GEN9(dev))
 		skl_wm_get_hw_state(dev);
-	else if (HAS_PCH_SPLIT(dev))
+	else if (HAS_PCH_SPLIT(dev_priv))
 		ilk_wm_get_hw_state(dev);
 
 	for_each_intel_crtc(dev, crtc) {
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index edaf35b975c0..0b6f1bab671d 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1336,13 +1336,14 @@  intel_dp_set_clock(struct intel_encoder *encoder,
 		   struct intel_crtc_state *pipe_config)
 {
 	struct drm_device *dev = encoder->base.dev;
+	struct drm_i915_private *dev_priv = to_i915(dev);
 	const struct dp_link_dpll *divisor = NULL;
 	int i, count = 0;
 
 	if (IS_G4X(dev)) {
 		divisor = gen4_dpll;
 		count = ARRAY_SIZE(gen4_dpll);
-	} else if (HAS_PCH_SPLIT(dev)) {
+	} else if (HAS_PCH_SPLIT(dev_priv)) {
 		divisor = pch_dpll;
 		count = ARRAY_SIZE(pch_dpll);
 	} else if (IS_CHERRYVIEW(dev)) {
@@ -1776,7 +1777,7 @@  static void intel_dp_prepare(struct intel_encoder *encoder,
 			intel_dp->DP |= DP_ENHANCED_FRAMING;
 
 		intel_dp->DP |= crtc->pipe << 29;
-	} else if (HAS_PCH_CPT(dev) && port != PORT_A) {
+	} else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
 		u32 trans_dp;
 
 		intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
@@ -1788,7 +1789,7 @@  static void intel_dp_prepare(struct intel_encoder *encoder,
 			trans_dp &= ~TRANS_DP_ENH_FRAMING;
 		I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
 	} else {
-		if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
+		if (!HAS_PCH_SPLIT(dev_priv) && !IS_VALLEYVIEW(dev) &&
 		    !IS_CHERRYVIEW(dev) && pipe_config->limited_color_range)
 			intel_dp->DP |= DP_COLOR_RANGE_16_235;
 
@@ -2442,7 +2443,7 @@  static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
 
 	if (IS_GEN7(dev) && port == PORT_A) {
 		*pipe = PORT_TO_PIPE_CPT(tmp);
-	} else if (HAS_PCH_CPT(dev) && port != PORT_A) {
+	} else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
 		enum pipe p;
 
 		for_each_pipe(dev_priv, p) {
@@ -2485,7 +2486,7 @@  static void intel_dp_get_config(struct intel_encoder *encoder,
 
 	pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
 
-	if (HAS_PCH_CPT(dev) && port != PORT_A) {
+	if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
 		u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
 
 		if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
@@ -2511,8 +2512,8 @@  static void intel_dp_get_config(struct intel_encoder *encoder,
 
 	pipe_config->base.adjusted_mode.flags |= flags;
 
-	if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
-	    !IS_CHERRYVIEW(dev) && tmp & DP_COLOR_RANGE_16_235)
+	if (!HAS_PCH_SPLIT(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
+	    !IS_CHERRYVIEW(dev_priv) && tmp & DP_COLOR_RANGE_16_235)
 		pipe_config->limited_color_range = true;
 
 	pipe_config->lane_count =
@@ -2659,7 +2660,7 @@  _intel_dp_set_link_train(struct intel_dp *intel_dp,
 		I915_WRITE(DP_TP_CTL(port), temp);
 
 	} else if ((IS_GEN7(dev) && port == PORT_A) ||
-		   (HAS_PCH_CPT(dev) && port != PORT_A)) {
+		   (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
 		*DP &= ~DP_LINK_TRAIN_MASK_CPT;
 
 		switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
@@ -2989,7 +2990,7 @@  intel_dp_voltage_max(struct intel_dp *intel_dp)
 		return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
 	else if (IS_GEN7(dev) && port == PORT_A)
 		return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
-	else if (HAS_PCH_CPT(dev) && port != PORT_A)
+	else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
 		return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
 	else
 		return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
@@ -3442,7 +3443,7 @@  intel_dp_link_down(struct intel_dp *intel_dp)
 	DRM_DEBUG_KMS("\n");
 
 	if ((IS_GEN7(dev) && port == PORT_A) ||
-	    (HAS_PCH_CPT(dev) && port != PORT_A)) {
+	    (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
 		DP &= ~DP_LINK_TRAIN_MASK_CPT;
 		DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
 	} else {
@@ -3464,7 +3465,7 @@  intel_dp_link_down(struct intel_dp *intel_dp)
 	 * to transcoder A after disabling it to allow the
 	 * matching HDMI port to be enabled on transcoder A.
 	 */
-	if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B && port != PORT_A) {
+	if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B && port != PORT_A) {
 		/*
 		 * We get CPU/PCH FIFO underruns on the other pipe when
 		 * doing the workaround. Sweep them under the rug.
@@ -5085,7 +5086,7 @@  intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
 	 * power sequencer any more. */
 	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 		port_sel = PANEL_PORT_SELECT_VLV(port);
-	} else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
+	} else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
 		if (port == PORT_A)
 			port_sel = PANEL_PORT_SELECT_DPA;
 		else
@@ -5649,7 +5650,7 @@  intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
 		intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
 	else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
 		intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
-	else if (HAS_PCH_SPLIT(dev))
+	else if (HAS_PCH_SPLIT(dev_priv))
 		intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
 	else
 		intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider;
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index d0c59c1793ef..c37ce1263142 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -1857,7 +1857,7 @@  void intel_shared_dpll_init(struct drm_device *dev)
 		dpll_mgr = &bxt_pll_mgr;
 	else if (HAS_DDI(dev_priv))
 		dpll_mgr = &hsw_pll_mgr;
-	else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
+	else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
 		dpll_mgr = &pch_pll_mgr;
 
 	if (!dpll_mgr) {
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 09b2146f157f..397e10f4b6f0 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -864,7 +864,7 @@  static void intel_hdmi_prepare(struct intel_encoder *encoder)
 	intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
 
 	hdmi_val = SDVO_ENCODING_HDMI;
-	if (!HAS_PCH_SPLIT(dev) && crtc->config->limited_color_range)
+	if (!HAS_PCH_SPLIT(dev_priv) && crtc->config->limited_color_range)
 		hdmi_val |= HDMI_COLOR_RANGE_16_235;
 	if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 		hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH;
@@ -879,7 +879,7 @@  static void intel_hdmi_prepare(struct intel_encoder *encoder)
 	if (crtc->config->has_hdmi_sink)
 		hdmi_val |= HDMI_MODE_SELECT_HDMI;
 
-	if (HAS_PCH_CPT(dev))
+	if (HAS_PCH_CPT(dev_priv))
 		hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);
 	else if (IS_CHERRYVIEW(dev))
 		hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe);
@@ -911,7 +911,7 @@  static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
 	if (!(tmp & SDVO_ENABLE))
 		goto out;
 
-	if (HAS_PCH_CPT(dev))
+	if (HAS_PCH_CPT(dev_priv))
 		*pipe = PORT_TO_PIPE_CPT(tmp);
 	else if (IS_CHERRYVIEW(dev))
 		*pipe = SDVO_PORT_TO_PIPE_CHV(tmp);
@@ -956,7 +956,7 @@  static void intel_hdmi_get_config(struct intel_encoder *encoder,
 	if (tmp & SDVO_AUDIO_ENABLE)
 		pipe_config->has_audio = true;
 
-	if (!HAS_PCH_SPLIT(dev) &&
+	if (!HAS_PCH_SPLIT(dev_priv) &&
 	    tmp & HDMI_COLOR_RANGE_16_235)
 		pipe_config->limited_color_range = true;
 
@@ -1141,7 +1141,7 @@  static void intel_disable_hdmi(struct intel_encoder *encoder,
 	 * to transcoder A after disabling it to allow the
 	 * matching DP port to be enabled on transcoder A.
 	 */
-	if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B) {
+	if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) {
 		/*
 		 * We get CPU/PCH FIFO underruns on the other pipe when
 		 * doing the workaround. Sweep them under the rug.
@@ -1896,7 +1896,7 @@  void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
 		intel_hdmi->write_infoframe = hsw_write_infoframe;
 		intel_hdmi->set_infoframes = hsw_set_infoframes;
 		intel_hdmi->infoframe_enabled = hsw_infoframe_enabled;
-	} else if (HAS_PCH_IBX(dev)) {
+	} else if (HAS_PCH_IBX(dev_priv)) {
 		intel_hdmi->write_infoframe = ibx_write_infoframe;
 		intel_hdmi->set_infoframes = ibx_set_infoframes;
 		intel_hdmi->infoframe_enabled = ibx_infoframe_enabled;
@@ -1929,6 +1929,7 @@  void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
 void intel_hdmi_init(struct drm_device *dev,
 		     i915_reg_t hdmi_reg, enum port port)
 {
+	struct drm_i915_private *dev_priv = to_i915(dev);
 	struct intel_digital_port *intel_dig_port;
 	struct intel_encoder *intel_encoder;
 	struct intel_connector *intel_connector;
@@ -1949,7 +1950,7 @@  void intel_hdmi_init(struct drm_device *dev,
 			 DRM_MODE_ENCODER_TMDS, "HDMI %c", port_name(port));
 
 	intel_encoder->compute_config = intel_hdmi_compute_config;
-	if (HAS_PCH_SPLIT(dev)) {
+	if (HAS_PCH_SPLIT(dev_priv)) {
 		intel_encoder->disable = pch_disable_hdmi;
 		intel_encoder->post_disable = pch_post_disable_hdmi;
 	} else {
@@ -1970,9 +1971,9 @@  void intel_hdmi_init(struct drm_device *dev,
 		intel_encoder->post_disable = vlv_hdmi_post_disable;
 	} else {
 		intel_encoder->pre_enable = intel_hdmi_pre_enable;
-		if (HAS_PCH_CPT(dev))
+		if (HAS_PCH_CPT(dev_priv))
 			intel_encoder->enable = cpt_enable_hdmi;
-		else if (HAS_PCH_IBX(dev))
+		else if (HAS_PCH_IBX(dev_priv))
 			intel_encoder->enable = ibx_enable_hdmi;
 		else
 			intel_encoder->enable = g4x_enable_hdmi;
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index 79aab9ad6faa..1410330ec9bb 100644
--- a/drivers/gpu/drm/i915/intel_i2c.c
+++ b/drivers/gpu/drm/i915/intel_i2c.c
@@ -633,7 +633,7 @@  int intel_setup_gmbus(struct drm_device *dev)
 	unsigned int pin;
 	int ret;
 
-	if (HAS_PCH_NOP(dev))
+	if (HAS_PCH_NOP(dev_priv))
 		return 0;
 
 	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
index 2e943bd1c3cf..baaf2ed897ef 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -106,7 +106,7 @@  static bool intel_lvds_get_hw_state(struct intel_encoder *encoder,
 	if (!(tmp & LVDS_PORT_EN))
 		goto out;
 
-	if (HAS_PCH_CPT(dev))
+	if (HAS_PCH_CPT(dev_priv))
 		*pipe = PORT_TO_PIPE_CPT(tmp);
 	else
 		*pipe = PORT_TO_PIPE(tmp);
@@ -396,7 +396,7 @@  static bool intel_lvds_compute_config(struct intel_encoder *intel_encoder,
 				      struct intel_crtc_state *pipe_config,
 				      struct drm_connector_state *conn_state)
 {
-	struct drm_device *dev = intel_encoder->base.dev;
+	struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
 	struct intel_lvds_encoder *lvds_encoder =
 		to_lvds_encoder(&intel_encoder->base);
 	struct intel_connector *intel_connector =
@@ -406,7 +406,7 @@  static bool intel_lvds_compute_config(struct intel_encoder *intel_encoder,
 	unsigned int lvds_bpp;
 
 	/* Should never happen!! */
-	if (INTEL_INFO(dev)->gen < 4 && intel_crtc->pipe == 0) {
+	if (INTEL_GEN(dev_priv) < 4 && intel_crtc->pipe == 0) {
 		DRM_ERROR("Can't support LVDS on pipe A\n");
 		return false;
 	}
@@ -431,7 +431,7 @@  static bool intel_lvds_compute_config(struct intel_encoder *intel_encoder,
 	intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
 			       adjusted_mode);
 
-	if (HAS_PCH_SPLIT(dev)) {
+	if (HAS_PCH_SPLIT(dev_priv)) {
 		pipe_config->has_pch_encoder = true;
 
 		intel_pch_panel_fitting(intel_crtc, pipe_config,
@@ -566,7 +566,7 @@  static int intel_lid_notify(struct notifier_block *nb, unsigned long val,
 	 * and as part of the cleanup in the hw state restore we also redisable
 	 * the vga plane.
 	 */
-	if (!HAS_PCH_SPLIT(dev))
+	if (!HAS_PCH_SPLIT(dev_priv))
 		intel_display_resume(dev);
 
 	dev_priv->modeset_restore = MODESET_DONE;
@@ -951,9 +951,11 @@  static bool compute_is_dual_link_lvds(struct intel_lvds_encoder *lvds_encoder)
 
 static bool intel_lvds_supported(struct drm_device *dev)
 {
+	struct drm_i915_private *dev_priv = to_i915(dev);
+
 	/* With the introduction of the PCH we gained a dedicated
 	 * LVDS presence pin, use it. */
-	if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
+	if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
 		return true;
 
 	/* Otherwise LVDS was only attached to mobile products,
@@ -997,14 +999,14 @@  void intel_lvds_init(struct drm_device *dev)
 	if (dmi_check_system(intel_no_lvds))
 		return;
 
-	if (HAS_PCH_SPLIT(dev))
+	if (HAS_PCH_SPLIT(dev_priv))
 		lvds_reg = PCH_LVDS;
 	else
 		lvds_reg = LVDS;
 
 	lvds = I915_READ(lvds_reg);
 
-	if (HAS_PCH_SPLIT(dev)) {
+	if (HAS_PCH_SPLIT(dev_priv)) {
 		if ((lvds & LVDS_DETECTED) == 0)
 			return;
 		if (dev_priv->vbt.edp.support) {
@@ -1068,7 +1070,7 @@  void intel_lvds_init(struct drm_device *dev)
 	intel_encoder->type = INTEL_OUTPUT_LVDS;
 	intel_encoder->port = PORT_NONE;
 	intel_encoder->cloneable = 0;
-	if (HAS_PCH_SPLIT(dev))
+	if (HAS_PCH_SPLIT(dev_priv))
 		intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
 	else if (IS_GEN4(dev))
 		intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
@@ -1158,7 +1160,7 @@  void intel_lvds_init(struct drm_device *dev)
 	 */
 
 	/* Ironlake: FIXME if still fail, not try pipe mode now */
-	if (HAS_PCH_SPLIT(dev))
+	if (HAS_PCH_SPLIT(dev_priv))
 		goto failed;
 
 	pipe = (lvds & LVDS_PIPEB_SELECT) ? 1 : 0;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index e7b3e6f39281..86051ef2716e 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7413,7 +7413,7 @@  static void ivybridge_init_clock_gating(struct drm_device *dev)
 	snpcr |= GEN6_MBC_SNPCR_MED;
 	I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
 
-	if (!HAS_PCH_NOP(dev))
+	if (!HAS_PCH_NOP(dev_priv))
 		cpt_init_clock_gating(dev);
 
 	gen6_check_mch_setup(dev);
@@ -7656,7 +7656,7 @@  void intel_init_clock_gating(struct drm_device *dev)
 
 void intel_suspend_hw(struct drm_device *dev)
 {
-	if (HAS_PCH_LPT(dev))
+	if (HAS_PCH_LPT(to_i915(dev)))
 		lpt_suspend_hw(dev);
 }
 
@@ -7732,7 +7732,7 @@  void intel_init_pm(struct drm_device *dev)
 		skl_setup_wm_latency(dev);
 		dev_priv->display.update_wm = skl_update_wm;
 		dev_priv->display.compute_global_watermarks = skl_compute_wm;
-	} else if (HAS_PCH_SPLIT(dev)) {
+	} else if (HAS_PCH_SPLIT(dev_priv)) {
 		ilk_setup_wm_latency(dev);
 
 		if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
index a061b0029797..0d9114f9ce27 100644
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -251,7 +251,7 @@  static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val)
 		 * HW workaround, need to write this twice for issue
 		 * that may result in first write getting masked.
 		 */
-		if (HAS_PCH_IBX(dev)) {
+		if (HAS_PCH_IBX(dev_priv)) {
 			I915_WRITE(intel_sdvo->sdvo_reg, val);
 			POSTING_READ(intel_sdvo->sdvo_reg);
 		}
@@ -1133,7 +1133,7 @@  static bool intel_sdvo_compute_config(struct intel_encoder *encoder,
 	DRM_DEBUG_KMS("forcing bpc to 8 for SDVO\n");
 	pipe_config->pipe_bpp = 8*3;
 
-	if (HAS_PCH_SPLIT(encoder->base.dev))
+	if (HAS_PCH_SPLIT(to_i915(encoder->base.dev)))
 		pipe_config->has_pch_encoder = true;
 
 	/* We need to construct preferred input timings based on our
@@ -1273,7 +1273,7 @@  static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder,
 		/* The real mode polarity is set by the SDVO commands, using
 		 * struct intel_sdvo_dtd. */
 		sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH;
-		if (!HAS_PCH_SPLIT(dev) && crtc_state->limited_color_range)
+		if (!HAS_PCH_SPLIT(dev_priv) && crtc_state->limited_color_range)
 			sdvox |= HDMI_COLOR_RANGE_16_235;
 		if (INTEL_INFO(dev)->gen < 5)
 			sdvox |= SDVO_BORDER_ENABLE;
@@ -1286,7 +1286,7 @@  static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder,
 		sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
 	}
 
-	if (INTEL_PCH_TYPE(dev) >= PCH_CPT)
+	if (INTEL_PCH_TYPE(dev_priv) >= PCH_CPT)
 		sdvox |= SDVO_PIPE_SEL_CPT(crtc->pipe);
 	else
 		sdvox |= SDVO_PIPE_SEL(crtc->pipe);
@@ -1339,7 +1339,7 @@  static bool intel_sdvo_get_hw_state(struct intel_encoder *encoder,
 	if (!(tmp & SDVO_ENABLE) && (active_outputs == 0))
 		return false;
 
-	if (HAS_PCH_CPT(dev))
+	if (HAS_PCH_CPT(dev_priv))
 		*pipe = PORT_TO_PIPE_CPT(tmp);
 	else
 		*pipe = PORT_TO_PIPE(tmp);
@@ -2997,7 +2997,7 @@  bool intel_sdvo_init(struct drm_device *dev,
 	}
 
 	intel_encoder->compute_config = intel_sdvo_compute_config;
-	if (HAS_PCH_SPLIT(dev)) {
+	if (HAS_PCH_SPLIT(dev_priv)) {
 		intel_encoder->disable = pch_disable_sdvo;
 		intel_encoder->post_disable = pch_post_disable_sdvo;
 	} else {