From patchwork Mon Oct 24 16:55:57 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Praveen Paneri X-Patchwork-Id: 9392657 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id A75CF60762 for ; Mon, 24 Oct 2016 16:51:50 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 987BE291AA for ; Mon, 24 Oct 2016 16:51:50 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 8CD1A291B1; Mon, 24 Oct 2016 16:51:50 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 1FDBE291AA for ; Mon, 24 Oct 2016 16:51:50 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5E4E56E569; Mon, 24 Oct 2016 16:51:49 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3363A6E55E for ; Mon, 24 Oct 2016 16:51:44 +0000 (UTC) Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga103.fm.intel.com with ESMTP; 24 Oct 2016 09:51:44 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.31,542,1473145200"; d="scan'208";a="23025987" Received: from intel-desktop.iind.intel.com ([10.223.82.55]) by fmsmga006.fm.intel.com with ESMTP; 24 Oct 2016 09:51:43 -0700 From: Praveen Paneri To: intel-gfx@lists.freedesktop.org Date: Mon, 24 Oct 2016 22:25:57 +0530 Message-Id: <1477328158-10817-3-git-send-email-praveen.paneri@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1477328158-10817-1-git-send-email-praveen.paneri@intel.com> References: <1477328158-10817-1-git-send-email-praveen.paneri@intel.com> Cc: Akash Goel Subject: [Intel-gfx] [PATCH 3/4] lib/igt_draw: Add Y-tiling support for IGT_DRAW_BLT method X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From: Akash Goel Signed-off-by: Akash Goel --- lib/igt_draw.c | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/lib/igt_draw.c b/lib/igt_draw.c index 29a725f..32600f0 100644 --- a/lib/igt_draw.c +++ b/lib/igt_draw.c @@ -31,6 +31,7 @@ #include "igt_core.h" #include "igt_fb.h" #include "ioctl_wrappers.h" +#include "i830_reg.h" /** * SECTION:igt_draw @@ -517,6 +518,23 @@ static void draw_rect_blt(int fd, struct cmd_data *cmd_data, blt_cmd_tiling = (tiling) ? XY_COLOR_BLT_TILED : 0; pitch = (tiling) ? buf->stride / 4 : buf->stride; + if (tiling == I915_TILING_Y) { + /* To change the tile register, insert an MI_FLUSH_DW followed by an MI_LOAD_REGISTER_IMM */ + BEGIN_BATCH(4, 0); + OUT_BATCH(MI_FLUSH_DW | 2); + OUT_BATCH(0x0); + OUT_BATCH(0x0); + OUT_BATCH(0x0); + ADVANCE_BATCH(); + + BEGIN_BATCH(4, 0); + OUT_BATCH(MI_LOAD_REGISTER_IMM); + OUT_BATCH(0x22200); /* BCS_SWCTRL */ + OUT_BATCH(((0x3 << 16) | 0x3)); /* enable the Y tiling */ + OUT_BATCH(MI_NOOP); + ADVANCE_BATCH(); + } + BEGIN_BATCH(6, 1); OUT_BATCH(XY_COLOR_BLT_CMD_NOLEN | XY_COLOR_BLT_WRITE_ALPHA | XY_COLOR_BLT_WRITE_RGB | blt_cmd_tiling | blt_cmd_len); @@ -527,6 +545,23 @@ static void draw_rect_blt(int fd, struct cmd_data *cmd_data, OUT_BATCH(color); ADVANCE_BATCH(); + if (tiling == I915_TILING_Y) { + /* To change the tile register, insert an MI_FLUSH_DW followed by an MI_LOAD_REGISTER_IMM */ + BEGIN_BATCH(4, 0); + OUT_BATCH(MI_FLUSH_DW | 2); + OUT_BATCH(0x0); + OUT_BATCH(0x0); + OUT_BATCH(0x0); + ADVANCE_BATCH(); + + BEGIN_BATCH(4, 0); + OUT_BATCH(MI_LOAD_REGISTER_IMM); + OUT_BATCH(0x22200); /* BCS_SWCTRL */ + OUT_BATCH((0x3 << 16)); /* Reset back to X-Tiling (default) */ + OUT_BATCH(MI_NOOP); + ADVANCE_BATCH(); + } + intel_batchbuffer_flush(batch); intel_batchbuffer_free(batch); }