From patchwork Tue Oct 25 23:36:52 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Dhinakaran Pandiyan X-Patchwork-Id: 9395709 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 53E7860234 for ; Tue, 25 Oct 2016 23:36:57 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1277E29666 for ; Tue, 25 Oct 2016 23:36:57 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 0699629698; Tue, 25 Oct 2016 23:36:57 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 6461429666 for ; Tue, 25 Oct 2016 23:36:56 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 90F026E22E; Tue, 25 Oct 2016 23:36:55 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id 967296E22E for ; Tue, 25 Oct 2016 23:36:54 +0000 (UTC) Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga102.jf.intel.com with ESMTP; 25 Oct 2016 16:36:54 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.31,399,1473145200"; d="scan'208,223";a="183819061" Received: from orsmsx105.amr.corp.intel.com ([10.22.225.132]) by fmsmga004.fm.intel.com with ESMTP; 25 Oct 2016 16:36:53 -0700 Received: from orsmsx151.amr.corp.intel.com (10.22.226.38) by ORSMSX105.amr.corp.intel.com (10.22.225.132) with Microsoft SMTP Server (TLS) id 14.3.248.2; Tue, 25 Oct 2016 16:36:53 -0700 Received: from orsmsx109.amr.corp.intel.com ([169.254.11.208]) by ORSMSX151.amr.corp.intel.com ([10.22.226.38]) with mapi id 14.03.0248.002; Tue, 25 Oct 2016 16:36:53 -0700 From: "Pandiyan, Dhinakaran" To: "Nikula, Jani" Thread-Topic: [Intel-gfx] [PATCH v2 2/2] drm/i915/dp: BDW cdclk fix for DP audio Thread-Index: AQHSLnbuRJmiB5pK1EmW62nE/GNXkKC5V5qAgAABIgCAAJ0KAIAAWImA Date: Tue, 25 Oct 2016 23:36:52 +0000 Message-ID: <1477439593.19344.38.camel@dk-H97M-D3H> References: <1477369117-24627-1-git-send-email-dhinakaran.pandiyan@intel.com> <1477369117-24627-3-git-send-email-dhinakaran.pandiyan@intel.com> <87funkokui.fsf@intel.com> <87d1iooknr.fsf@intel.com> <1477420580.19344.10.camel@dk-H97M-D3H> In-Reply-To: <1477420580.19344.10.camel@dk-H97M-D3H> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: yes X-MS-TNEF-Correlator: x-originating-ip: [10.54.75.26] MIME-Version: 1.0 Cc: "libin.yang@linux.intel.com" , "Kp, Jeeja" , "intel-gfx@lists.freedesktop.org" , "Zanoni, Paulo R" Subject: Re: [Intel-gfx] [PATCH v2 2/2] drm/i915/dp: BDW cdclk fix for DP audio X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP On Tue, 2016-10-25 at 18:19 +0000, Pandiyan, Dhinakaran wrote: > On Tue, 2016-10-25 at 12:14 +0300, Jani Nikula wrote: > > On Tue, 25 Oct 2016, Jani Nikula wrote: > > > On Tue, 25 Oct 2016, Dhinakaran Pandiyan wrote: > > >> According to BSpec, cdclk has to be not less than 432 MHz with DP audio > > >> enabled, port width x4, and link rate HBR2 (5.4 GHz) > > >> > > >> Having a lower cdclk triggers pipe underruns, which then lead to displays > > >> continuously cycling off and on. This is essential for DP MST audio as the > > >> link is trained at HBR2 and 4 lanes by default. > > >> > > >> v2: Restrict fix to BDW > > >> Retain the set cdclk across modesets (Ville) > > > > > > Cc: stable@vger.kernel.org > > > > > >> > > >> Signed-off-by: Dhinakaran Pandiyan > > >> --- > > >> drivers/gpu/drm/i915/intel_display.c | 28 +++++++++++++++++++++++++--- > > >> 1 file changed, 25 insertions(+), 3 deletions(-) > > >> > > >> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > > >> index a94f7d1..8c59651 100644 > > >> --- a/drivers/gpu/drm/i915/intel_display.c > > >> +++ b/drivers/gpu/drm/i915/intel_display.c > > >> @@ -10260,6 +10260,18 @@ static void bxt_modeset_commit_cdclk(struct drm_atomic_state *old_state) > > >> bxt_set_cdclk(to_i915(dev), req_cdclk); > > >> } > > >> > > >> +static unsigned int bdw_dp_audio_cdclk(struct intel_crtc_state *crtc_state) > > >> +{ > > >> + > > >> + if (intel_crtc_has_dp_encoder(crtc_state) && > > >> + crtc_state->has_audio && > > >> + crtc_state->port_clock >= 540000 && > > >> + crtc_state->lane_count == 4) > > >> + return 432000; > > > > > > Where does 432000 come from? 450000 or even (337500 + 1). See below. > > > > > >> + > > >> + return 0; > > >> +} > > >> + > > >> /* compute the max rate for new configuration */ > > >> static int ilk_max_pixel_rate(struct drm_atomic_state *state) > > >> { > > >> @@ -10275,7 +10287,7 @@ static int ilk_max_pixel_rate(struct drm_atomic_state *state) > > >> sizeof(intel_state->min_pixclk)); > > >> > > >> for_each_crtc_in_state(state, crtc, cstate, i) { > > >> - int pixel_rate; > > >> + unsigned int pixel_rate; > > >> > > >> crtc_state = to_intel_crtc_state(cstate); > > >> if (!crtc_state->base.enable) { > > >> @@ -10285,9 +10297,19 @@ static int ilk_max_pixel_rate(struct drm_atomic_state *state) > > >> > > >> pixel_rate = ilk_pipe_pixel_rate(crtc_state); > > >> > > >> + if (IS_BROADWELL(dev_priv)) { > > >> /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ > > >> - if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)432 > > >> - pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95); > > >> + if (crtc_state->ips_enabled) > > >> + pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95); > > >> + > > >> + /* BSpec says "Do not use DisplayPort with CDCLK less than > > >> + * 432 MHz, audio enabled, port width x4, and link rate > > > > > > For me the spec says "Do not use DisplayPort with CDCLK 337.5 MHz", not > > > "less than 432 MHz". > > > > Right, so the spec for *Skylake* mentions 432 MHz. Now, we need this fix > > for both Broadwell and Skylake, where's the Skylake part? > > > > BR, > > Jani. > > > > > > I believe you are looking at CDCLK_CTL that refers to pre-production SKL > SKU's. See the description for DP_TP_CTL instead. The information seems > to be scattered a bit > > > > > > > >> + * HBR2 (5.4 GHz), or else there may be audio corruption or > > >> + * screen corruption." > > >> + */ > > >> + pixel_rate = max(pixel_rate, > > >> + bdw_dp_audio_cdclk(crtc_state)); > > >> + } > > > > > > I'd add a new function > > > > > > static int bwd_adjust_min_pipe_pixel_rate(struct intel_crtc_state *crtc_state, > > > int pixel_rate) > > > > > > and do both the IPS adjustment and the audio adjustment there, returning > > > the original pixel_rate if adjustment is not needed. Move the comments > > > there as well. > > > > > > It would be called as > > > > > > if (IS_BROADWELL(dev_priv)) > > > pixel_rate = bwd_adjust_min_pipe_pixel_rate(crtc_state, pixel_rate); > > > > > > here. > > > > > > > > > BR, > > > Jani. > > > > > Will do. > > -DK > > >> > > >> intel_state->min_pixclk[i] = pixel_rate; > > >> } > > > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx From 418d4a849252e8faa6d4e4403f5a99765f343833 Mon Sep 17 00:00:00 2001 From: Dhinakaran Pandiyan Date: Mon, 24 Oct 2016 16:24:20 -0700 Subject: [PATCH v3 2/2] drm/i915/dp: BDW cdclk fix for DP audio MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit According to BSpec, cdclk has to be not less than 432 MHz with DP audio enabled, port width x4, and link rate HBR2 (5.4 GHz) Having a lower cdclk triggers pipe underruns, which then lead to displays continuously cycling off and on. This is essential for DP MST audio as the link is trained at HBR2 and 4 lanes by default. v3: Combine BDW pixel rate adjustments into a function (Jani) v2: Restrict fix to BDW Retain the set cdclk across modesets (Ville) Cc: stable@vger.kernel.org Signed-off-by: Dhinakaran Pandiyan Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/i915/intel_display.c | 27 ++++++++++++++++++++++++--- 1 file changed, 24 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index a94f7d1..efe46b4 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -10260,6 +10260,27 @@ static void bxt_modeset_commit_cdclk(struct drm_atomic_state *old_state) bxt_set_cdclk(to_i915(dev), req_cdclk); } +static int bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state *crtc_state, + int pixel_rate) +{ + /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ + if (crtc_state->ips_enabled) + pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95); + + /* BSpec says "Do not use DisplayPort with CDCLK less than + * 432 MHz, audio enabled, port width x4, and link rate + * HBR2 (5.4 GHz), or else there may be audio corruption or + * screen corruption." + */ + if (intel_crtc_has_dp_encoder(crtc_state) && + crtc_state->has_audio && + crtc_state->port_clock >= 540000 && + crtc_state->lane_count == 4) + pixel_rate = max(432000, pixel_rate); + + return pixel_rate; +} + /* compute the max rate for new configuration */ static int ilk_max_pixel_rate(struct drm_atomic_state *state) { @@ -10285,9 +10306,9 @@ static int ilk_max_pixel_rate(struct drm_atomic_state *state) pixel_rate = ilk_pipe_pixel_rate(crtc_state); - /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ - if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled) - pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95); + if (IS_BROADWELL(dev_priv)) + pixel_rate = bdw_adjust_min_pipe_pixel_rate(crtc_state, + pixel_rate); intel_state->min_pixclk[i] = pixel_rate; } -- 2.7.4