diff mbox

[11/15] drm/i915/glk: Update Port PLL enable sequence for Geminilkae

Message ID 1478791400-21756-12-git-send-email-ander.conselvan.de.oliveira@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Ander Conselvan de Oliveira Nov. 10, 2016, 3:23 p.m. UTC 
From: Madhav Chauhan <madhav.chauhan@intel.com>

Add steps for enabling and disabling Port PLL as per bspec.

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h       |  2 ++
 drivers/gpu/drm/i915/intel_dpll_mgr.c | 20 ++++++++++++++++++++
 2 files changed, 22 insertions(+)

Comments

Rodrigo Vivi Dec. 2, 2016, 12:44 a.m. UTC | #1 
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

On Thu, Nov 10, 2016 at 05:23:16PM +0200, Ander Conselvan de Oliveira wrote:
> From: Madhav Chauhan <madhav.chauhan@intel.com>
> 
> Add steps for enabling and disabling Port PLL as per bspec.
> 
> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h       |  2 ++
>  drivers/gpu/drm/i915/intel_dpll_mgr.c | 20 ++++++++++++++++++++
>  2 files changed, 22 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 88f9f2b..98e24a7 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1238,6 +1238,8 @@ enum skl_disp_power_wells {
>  #define   PORT_PLL_ENABLE		(1 << 31)
>  #define   PORT_PLL_LOCK			(1 << 30)
>  #define   PORT_PLL_REF_SEL		(1 << 27)
> +#define   PORT_PLL_POWER_ENABLE		(1 << 26)
> +#define   PORT_PLL_POWER_STATE		(1 << 25)
>  #define BXT_PORT_PLL_ENABLE(port)	_MMIO_PORT(port, _PORT_PLL_A, _PORT_PLL_B)
>  
>  #define _PORT_PLL_EBB_0_A		0x162034
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> index 24a28b2..35f5f1a 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> @@ -1381,6 +1381,16 @@ static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv,
>  	temp |= PORT_PLL_REF_SEL;
>  	I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
>  
> +	if (IS_GEMINILAKE(dev_priv)) {
> +		temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
> +		temp |= PORT_PLL_POWER_ENABLE;
> +		I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
> +
> +		if (wait_for_us((I915_READ(BXT_PORT_PLL_ENABLE(port)) &
> +				 PORT_PLL_POWER_STATE), 200))
> +			DRM_ERROR("Power state not set for PLL:%d\n", port);
> +	}
> +
>  	/* Disable 10 bit clock */
>  	temp = I915_READ(BXT_PORT_PLL_EBB_4(phy, ch));
>  	temp &= ~PORT_PLL_10BIT_CLK_ENABLE;
> @@ -1486,6 +1496,16 @@ static void bxt_ddi_pll_disable(struct drm_i915_private *dev_priv,
>  	temp &= ~PORT_PLL_ENABLE;
>  	I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
>  	POSTING_READ(BXT_PORT_PLL_ENABLE(port));
> +
> +	if (IS_GEMINILAKE(dev_priv)) {
> +		temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
> +		temp &= ~PORT_PLL_POWER_ENABLE;
> +		I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
> +
> +		if (wait_for_us(!(I915_READ(BXT_PORT_PLL_ENABLE(port)) &
> +				PORT_PLL_POWER_STATE), 200))
> +			DRM_ERROR("Power state not reset for PLL:%d\n", port);
> +	}
>  }
>  
>  static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
> -- 
> 2.5.5
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 88f9f2b..98e24a7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1238,6 +1238,8 @@  enum skl_disp_power_wells {
 #define   PORT_PLL_ENABLE		(1 << 31)
 #define   PORT_PLL_LOCK			(1 << 30)
 #define   PORT_PLL_REF_SEL		(1 << 27)
+#define   PORT_PLL_POWER_ENABLE		(1 << 26)
+#define   PORT_PLL_POWER_STATE		(1 << 25)
 #define BXT_PORT_PLL_ENABLE(port)	_MMIO_PORT(port, _PORT_PLL_A, _PORT_PLL_B)
 
 #define _PORT_PLL_EBB_0_A		0x162034
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index 24a28b2..35f5f1a 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -1381,6 +1381,16 @@  static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv,
 	temp |= PORT_PLL_REF_SEL;
 	I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
 
+	if (IS_GEMINILAKE(dev_priv)) {
+		temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
+		temp |= PORT_PLL_POWER_ENABLE;
+		I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
+
+		if (wait_for_us((I915_READ(BXT_PORT_PLL_ENABLE(port)) &
+				 PORT_PLL_POWER_STATE), 200))
+			DRM_ERROR("Power state not set for PLL:%d\n", port);
+	}
+
 	/* Disable 10 bit clock */
 	temp = I915_READ(BXT_PORT_PLL_EBB_4(phy, ch));
 	temp &= ~PORT_PLL_10BIT_CLK_ENABLE;
@@ -1486,6 +1496,16 @@  static void bxt_ddi_pll_disable(struct drm_i915_private *dev_priv,
 	temp &= ~PORT_PLL_ENABLE;
 	I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
 	POSTING_READ(BXT_PORT_PLL_ENABLE(port));
+
+	if (IS_GEMINILAKE(dev_priv)) {
+		temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
+		temp &= ~PORT_PLL_POWER_ENABLE;
+		I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
+
+		if (wait_for_us(!(I915_READ(BXT_PORT_PLL_ENABLE(port)) &
+				PORT_PLL_POWER_STATE), 200))
+			DRM_ERROR("Power state not reset for PLL:%d\n", port);
+	}
 }
 
 static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,