From patchwork Wed Nov 23 16:18:27 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Manna, Animesh" X-Patchwork-Id: 9443699 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id AE3A26075F for ; Wed, 23 Nov 2016 16:05:56 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B0D1227A98 for ; Wed, 23 Nov 2016 16:05:56 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id A5AE327B2F; Wed, 23 Nov 2016 16:05:56 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 5264827A98 for ; Wed, 23 Nov 2016 16:05:56 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3579D6E8E9; Wed, 23 Nov 2016 16:05:52 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id 933836E8E5 for ; Wed, 23 Nov 2016 16:05:49 +0000 (UTC) Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga101.fm.intel.com with ESMTP; 23 Nov 2016 08:05:26 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.31,538,1473145200"; d="scan'208";a="194936169" Received: from dispdev.iind.intel.com ([10.223.25.80]) by fmsmga004.fm.intel.com with ESMTP; 23 Nov 2016 08:05:24 -0800 From: Animesh Manna To: intel-gfx@lists.freedesktop.org Date: Wed, 23 Nov 2016 21:48:27 +0530 Message-Id: <1479917907-2468-6-git-send-email-animesh.manna@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1479917907-2468-1-git-send-email-animesh.manna@intel.com> References: <1479917907-2468-1-git-send-email-animesh.manna@intel.com> Subject: [Intel-gfx] [PATCH 5/5] drm/i915: Enable HPD interrupts with master ctl interrupt X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP While suspending the device hpd related interrupts are enabled to get the interrupt when device is in suspend state. Though display is in DC9 but system can be in S0 or S0i3 state. Hot plug during S0 state will generate de_port_interrupt but if system is in S0i3 state then display driver will get hotplug interrupt as pcu_hpd_interrupt which will come via pmc. So added the interrupt handling for pcu hpd interrupt. Signed-off-by: Animesh Manna Signed-off-by: A.Sunil Kamath --- drivers/gpu/drm/i915/i915_irq.c | 56 ++++++++++++++++++++++++++++++++++++++--- drivers/gpu/drm/i915/i915_reg.h | 12 +++++++++ 2 files changed, 65 insertions(+), 3 deletions(-) mode change 100644 => 100755 drivers/gpu/drm/i915/i915_irq.c diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c old mode 100644 new mode 100755 index cb8a75f..2f9b604 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -110,9 +110,9 @@ /* BXT hpd list */ static const u32 hpd_bxt[HPD_NUM_PINS] = { - [HPD_PORT_A] = BXT_DE_PORT_HP_DDIA, - [HPD_PORT_B] = BXT_DE_PORT_HP_DDIB, - [HPD_PORT_C] = BXT_DE_PORT_HP_DDIC + [HPD_PORT_A] = (BXT_DE_PORT_HP_DDIA | BXT_PCU_DC9_HP_DDIA), + [HPD_PORT_B] = (BXT_DE_PORT_HP_DDIB | BXT_PCU_DC9_HP_DDIB), + [HPD_PORT_C] = (BXT_DE_PORT_HP_DDIC | BXT_PCU_DC9_HP_DDIC) }; /* IIR can theoretically queue up two events. Be paranoid. */ @@ -2463,6 +2463,24 @@ static void bxt_hpd_irq_handler(struct drm_i915_private *dev_priv, DRM_ERROR("The master control interrupt lied (DE PORT)!\n"); } + if (master_ctl & GEN8_PCU_IRQ) { + iir = I915_READ(GEN8_PCU_IIR); + if (iir) { + u32 tmp_mask; + + I915_WRITE(GEN8_PCU_IIR, iir); + ret = IRQ_HANDLED; + if (IS_BROXTON(dev_priv)) { + tmp_mask = iir & BXT_PCU_DC9_HOTPLUG_MASK; + if (tmp_mask) + bxt_hpd_irq_handler(dev_priv, tmp_mask, + hpd_bxt); + } else + DRM_ERROR("Unexpected PCU interrupt\n"); + } else + DRM_ERROR("The master control interrupt lied (PCU)!\n"); + } + for_each_pipe(dev_priv, pipe) { u32 flip_done, fault_errors; @@ -4294,6 +4312,19 @@ void intel_irq_uninstall(struct drm_i915_private *dev_priv) dev_priv->pm.irqs_enabled = false; } +static void bxt_enable_pcu_interrupt(struct drm_i915_private *dev_priv) +{ + u32 de_pcu_hpd_enable_mask, de_pcu_imr, de_pcu_ier; + + de_pcu_hpd_enable_mask = GEN9_DE_PCU_PORTA_HOTPLUG | + GEN9_DE_PCU_PORTB_HOTPLUG | + GEN9_DE_PCU_PORTC_HOTPLUG; + + de_pcu_imr = (I915_READ(GEN8_PCU_IMR) & 0x0); + de_pcu_ier = (I915_READ(GEN8_PCU_IER) | de_pcu_hpd_enable_mask); + GEN5_IRQ_INIT(GEN8_PCU_, de_pcu_imr, de_pcu_ier); +} + /** * intel_runtime_pm_disable_interrupts - runtime interrupt disabling * @dev_priv: i915 device instance @@ -4303,8 +4334,27 @@ void intel_irq_uninstall(struct drm_i915_private *dev_priv) */ void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv) { + unsigned long flags = 0; + dev_priv->drm.driver->irq_uninstall(&dev_priv->drm); dev_priv->pm.irqs_enabled = false; + + if (IS_BROXTON(dev_priv) && dev_priv->vbt.hpd_wakeup_enabled) { + + /* Enable HPD related interrupts during DC9 for HPD wakeup */ + + I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL); + POSTING_READ(GEN8_MASTER_IRQ); + + spin_lock_irqsave(&dev_priv->irq_lock, flags); + if (dev_priv->display.hpd_irq_setup) + dev_priv->display.hpd_irq_setup(dev_priv); + spin_unlock_irqrestore(&dev_priv->irq_lock, flags); + + bxt_enable_pcu_interrupt(dev_priv); + + dev_priv->pm.irqs_enabled = true; + } synchronize_irq(dev_priv->drm.irq); } diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 3361d7f..df89025 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -6030,6 +6030,18 @@ enum { #define GEN8_PCU_IIR _MMIO(0x444e8) #define GEN8_PCU_IER _MMIO(0x444ec) +/* BXT PCU DC9 hotplug control */ +#define BXT_PCU_DC9_HP_DDIA (1<<31) +#define BXT_PCU_DC9_HP_DDIB (1<<30) +#define BXT_PCU_DC9_HP_DDIC (1<<29) +#define BXT_PCU_DC9_HOTPLUG_MASK (BXT_PCU_DC9_HP_DDIA | \ + BXT_PCU_DC9_HP_DDIB | \ + BXT_PCU_DC9_HP_DDIC) + +#define GEN9_DE_PCU_PORTA_HOTPLUG (1 << 31) +#define GEN9_DE_PCU_PORTB_HOTPLUG (1 << 30) +#define GEN9_DE_PCU_PORTC_HOTPLUG (1 << 29) + #define ILK_DISPLAY_CHICKEN2 _MMIO(0x42004) /* Required on all Ironlake and Sandybridge according to the B-Spec. */ #define ILK_ELPIN_409_SELECT (1 << 25)